AN82527F8 Intel, AN82527F8 Datasheet - Page 20

• Manufacturer Part Number: AN82527F8
• Description: IC CAN CONTRL 5V AUTOTEMP 44PLCC
• Manufacturer: Intel

Specifications of AN82527F8

• Rohs Status: RoHS non-compliant
• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 50mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 820732

82527
15 Page 7 t
16 Page 3 RESET
17 Page 2 Figure 2 Pin 7 name changed to
18 Page 4
19 Page 5 ABSOLUTE MAXIMUM RATINGS addi-
20 Page 12 t
21 Page 14 t
22 Page 7 t
23 Page 7 t
This is the -003 revision of the 82527 data sheet
The following differences exist between the -002
version and the -003 revision
20
1 The data sheet has been revised to ADVANCE
2 ABSOLUTE MAXIMUM RATINGS have been
3 V
4 V
5 I
6 Note 2 was added stating during I
7 t
Warm reset (V
is asserted) RESET
low level for 1 ms minimum
Cold reset (V
RESET
low for 1 ms minimum measured from a valid
V
required during a cold reset event
(WR
(WR
and WR
16-bit Intel mode replaces the description WR
used for Intel modes
tion Laboratory testing shows the 82527 will
withstand up to 10 mA for injected current into
both RX0 and RX1 pins for a total of 20 days
without sustaining permanent damage This
high current condition may be the result of
shorted signal lines The 82527 will not function
properly if the RX0 RX1 input voltage exceeds
V
from PRELIMINARY indicating the specifica-
tions have been verified through electrical tests
added
CPU Interface mode 3
age for AD0 – AD7 pins in CPU Interface mode 3
as
from 100 mA
pins are driven to V
and RX1
CC
AVLL
CC
CC
IL
IL1
b
no longer applies to the AD0 – AD7 pins in
supply current has been reduced to 50 mA
has been added to specify Input Low Volt-
a
level No falling edge on the reset pin is
0 5V minimum and
has been decreased to 20 ns from 33 ns
WRL ) (R W ) from WR
WRL ) (R W ) from WR
0 5V
WHQX
CLLL
AVLL
is asserted RESET
CHDV
ELDV
pin description name changed to
in 8-bit Intel mode and WRL
CC
decreased from 20 ns to 10 ns
decreased from 20 ns to 7 5 ns
CC
decreased from 20 ns to 12 5 ns
decreased from 25 ns to 15 ns
decreased from 25 ns to 15 ns
is driven to a valid level while
description addition
remains valid while RESET
SS
must be driven to a valid
or V
a
0 5V maximum
CC
must be driven
including RX0
PD
(R W )
testing all
(R W )
in
10 t
11 t
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 The t
20 t
21 The input voltage in the A C Testing Input Dia-
8 t
9 t
ns from 2 t
without a previous Write (Modes 0 1)
t
ns from 4 t
a previous Write (Modes 0 1)
for a 32 ns delay t
(Modes 0 1)
100 ns from 2 t
100 ns from 2 t
without a previous Write (Mode 2)
t
100 ns from 4 t
with a previous Write (Mode 2)
2 t
(Mode 3)
from V
states an on-chip pullup will drive DSACK0
approximately 2 4V An external pullup is re-
quired to drive this signal to a higher voltage
(Mode 3)
t
Invalid (Mode 3)
High to R W
for Reads of the High Speed Registers (Mode
3)
100 ns from 2 t
without a previous Write (Mode 3)
t
100 ns from 4 t
with a previous Write (Mode 3)
ed to t
(Mode 3)
gram have been revised to V
3 0V (high level) and revised to 0 1V from 0 8V
(low level)
RLDV1
RLDV1
CLYV
WHYZ
EHDV
EHDV
ELEL
CLDV
CHKH
CHAI
CHAI
CHRI
EHDV
EHDV
EHDV
CHAI
MCLK
AVAL
has been increased to 10 ns from 5 ns
no longer includes CS
has been increased to 10 ns from 5 ns
has been decreased to 55 ns from 65 ns
e
has added the condition of V
has been decreased to 2 t
IH
has been decreased to 55 ns from 65 ns
AVAV
is specified for V
has been decreased to 1 5 t
has been decreased to 3 5 t
has been decreased to 1 5 t
has been decreased to 3 5 t
has been decreased to 1 5 t
has been decreased to 3 5 t
has been decreased to 2 t
a
e
5 ns has been added to specify CS
MCLK
specification name has been correct-
145 ns (Mode 2)
MCLK
3 0V Note 3 has been added which
(Mode 3)
MCLK
MCLK
MCLK
MCLK
MCLK
Invalid (Mode 3)
a
a
CLYV
100 ns for a Read Cycle with
a
a
a
a
100 ns for a Read Cycle
a
100 ns for a Read Cycle
100 ns for a Read Cycle
100 ns for a Read Cycle
100 ns for a Read Cycle
is 40 ns for V
145 ns (Modes 0 1)
IH
e
CC
2 4V decreased
High to R W
b
MCLK
MCLK
OL
MCLK
OL
0 5V from
MCLK
MCLK
MCLK
MCLK
MCLK
e
e
a
a
1 0V
from
0 45
100
100
a
a
a
a
a
to