AN82527F8 Intel, AN82527F8 Datasheet - Page 21

• Manufacturer Part Number: AN82527F8
• Description: IC CAN CONTRL 5V AUTOTEMP 44PLCC
• Manufacturer: Intel

Specifications of AN82527F8

• Rohs Status: RoHS non-compliant
• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 50mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 820732

The following differences exist between the -001
version and the -002 revision
10 I
11 The following note was added to the electrical
12 The following D C Characteristics Specifica-
1 The RAM block in Figure 1 82527 Block Dia-
2 The INT
3 The Mode0 and Mode1 pin descriptions were
4 The DSACK0
5 V
6 V
7 V
8 I
9 I
gram was previously called DPRAM
Package and in other descriptions was previ-
ously called the INT
modified to include the following note These
pins are weakly held low during reset
reflect an open-drain output
added
added
corrected from 700
maximum
corrected from 100
maximum
to 25 A maximum
characteristics Port pins are weakly held high
after reset until the port configuration registers
are written (9FH AFH)
tions have been removed and replaced by the
Internal Delay 1 and Internal Delay 2 specifica-
tions These specifications reflect the produc-
tion test methodology which requires these two
delays to be tested together
SLEEP
SLEEP
PD
a Delay Dominant to Recessive
b Delay Recessive to Dominant
c Input Delay with Comparator Bypassed
d Rise Time
e Fall Time
IL1
IH1
IH2
current was changed from 10
for RX0 in comparator bypass mode was
hysteresis on RESET
for RX0 in comparator bypass mode was
current with V
current with V
(V
CC
pin description was changed to
2) pin in Figure 2 44-Pin PLCC
CC
CC
(V
A minimum to 700
A minimum to 100
DD
2 output disabled was
2 output enabled was
2) pin
was added
A minimum
A
A
13 The following A C Characteristics for 8-Bit
16-Bit Multiplexed Intel Modes (Modes 0 1)
have been changed
m The following definition was added for a
b t
d t
e t
h t
n The following definition was added for a
a 1 t
c t
g t
k t
f t
j t
l The following note was added References
i t
5 MHz
22 5 ns
0 ns
the READY pin is an open-drain output
flect the READY pin is an open-drain output
the READY pin is an open-drain output
250 ns from 2 t
to WR
‘‘read cycle without a previous write’’ The
time between the rising edge of WR
WRH
falling edge of RD
cle) is greater than 2 t
‘‘write cycle with a previous write’’ The time
between the rising edge of WR
(for the previous write cycle) and the next
rising edge of WR
write cycle) is less than 2 t
LLAX
LLRL
CLLL
WHLH
WHCH
RLDV1
WLYH
WHYH
RLYH
WHDV
MCLK
has been added
has been decreased to 20 ns from
has been increased to 20 ns from
has been changed to t
has been changed to t
has been increased to 8 ns from 0 ns
has been added
has been added
has been changed to t
has been increased to 2 t
(for the previous write cycle) and the
has been increased to 8 MHz from
also pertain to WRH
MCLK
(for the current read cy-
WRH
a
MCLK
100 ns
MCLK
(for the current
WLYZ
RLYZ
WHYZ
to reflect
to reflect
MCLK
WRH
82527
to re-
21
a