AN82527F8 Intel, AN82527F8 Datasheet - Page 4

• Manufacturer Part Number: AN82527F8
• Description: IC CAN CONTRL 5V AUTOTEMP 44PLCC
• Manufacturer: Intel

Specifications of AN82527F8

• Rohs Status: RoHS non-compliant
• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 50mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 820732

82527
PIN DESCRIPTION
The 82527 pins are described in this section Table 1 presents the legend for interpreting the pin types
PIN DESCRIPTIONS
4
Pin Name
V
V
V
XTAL1
XTAL2
CLKOUT
RESET
CS
INT
(V
RX0
RX1
TX0
TX1
SS1
SS2
CC
CC
2)
Pin Type
Ground
Ground
Power
O
O
O
O
O
O
I
I
I
I
I
GROUND connection must be connected externally to a V
Provides digital ground
GROUND connection must be connected externally to a V
Provides ground for analog comparator
POWER connection must be connected externally to
for entire device
Input for an external clock XTAL1 (along with XTAL2) are the crystal
connections to an internal oscillator
Push-pull output from the internal oscillator XTAL2 (along with XTAL1) are the
crystal connections to an internal oscillator If an external oscillator is used
XTAL2 must be floated or not be connected XTAL2 must not be used as a
clock output to drive other CPUs
Programmable clock output This output may be used to drive the oscillator of
the host microcontroller
Warm Reset (V
driven to a valid low level for 1 ms minimum
Cold Reset (V
must be driven low for 1 ms minimum measured from a valid V
falling edge on the reset pin is required during a cold reset event
A low level on this pin enables CPU access to the 82527 device
The interrupt pin is an open-drain output to the host microcontroller V
the power supply for the ISO low speed physical layer The function of this pin is
determined by the MUX bit in the CPU Interface Register (Address 02H) as
follows
Inputs from the CAN bus line(s) to the input comparator A recessive level is
read when RX0
CoBy bit (Bus Configuration register) is programmed as a ‘‘1’’ the input
comparator is bypassed and RX0 is the CAN bus line input
Serial data push-pull output to the CAN bus line During a recessive bit TX0 is
high and TX1 is low During a dominant bit TX0 is low and TX1 is high
MUX
MUX
Symbol
I O
O
e
e
I
1 pin 24 (PLCC)
0 pin 24 (PLCC)
Table 1 Pin Type Legend
CC
CC
l
Input only pin
Output only pin
Pin can be either input or output
is driven to a valid level while RESET
RX1 A dominant level is read when RX1
remains valid while RESET
Description
e
e
V
INT
Pin Description
CC
2 pin 11
e
is asserted) RESET
INT
a
5V DC Provides power
is asserted) RESET
SS
SS
l
board plane
board plane
CC
RX0 When the
level No
CC
must be
2 is