DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 28

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

3.0 Functional Description
With Priority Queueing, the device will transfer packets
onto up to 4 Descriptor lists. The device has four descriptor
pointers and associated control logic to keep track of when
descriptors are available with valid packet information. The
Receiver uses the user_priority field of a VLAN tag to
determine the priority, based on the 802.1Q encodings
based on the number of priority queues enabled. If the
Inputs to the receive state machine include the following events:
Q0
Q1
Q2
Q3
The receive state machine manipulates the fol-
lowing internal data spaces:
link
bufptr
cmdsts
link
bufptr
cmdsts
link
bufptr
cmdsts
link
bufptr
cmdsts
RxDescCache
rxDescRead
rxDescWrite
rxFragWrite
rxDescRefr
rxPktBytes
rxFifoBlock
CR:RXEN
XferDone
rxPktCnt
descCnt
fragPtr
RXDP
CRDD
rxIdle
Figure 3-18 Receive Architecture with Priority Queueing
link
bufptr
cmdsts
link
bufptr
cmdsts
link
bufptr
cmdsts
link
bufptr
cmdsts
Receive Descriptor List
The RXEN bit in the Command Register has been set.
completion of a PCI bus transfer request.
A 32- or 64-bit register that points to the current receive descriptor.
An internal bit flag that is set when the current receive descriptor has been completed, and
ownership has been returned to the driver. It is cleared whenever RXDP is loaded with a new
value (either by the state machine, or the driver).
An internal data space equal to the size of the maximum receive descriptor supported.
Count of bytes available for storing receive data in all of the fragments described by the current
descriptor.
Pointer to the next unwritten byte in the current fragment.
Number of packets in the rxDataFifo. Incremented by the MAC (the fill side of the FIFO).
Decremented by the receive state machine as packets are processed.
Number of bytes in the current packet being drained from the rxDataFifo, that are in fact
currently in the rxDataFifo (Note: for packets larger than the FIFO size, this number will never
be greater than the FIFO size).
The receive state machine is idle.
Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus.
Waiting for the transfer of a descriptor from the PCI bus into the RxDescCache.
Waiting for the amount of data in the RxDataFifo to reach the RxDrainThreshold or to
represent a complete packet.
Waiting for the transfer of data from the RxDataFIFO via the PCI bus to host memory.
Waiting for the completion of the write of the cmdsts field of a receive descriptor.
(Continued)
Software/Memory
link
bufptr
cmdsts
link
bufptr
cmdsts
link
bufptr
cmdsts
link
bufptr
cmdsts
28
packet has no VLAN tag, then a priority of 0 is assumed.
There is no reordering of packets while in the Receive Data
FIFO.
3.13.5 Receive State Machine
The receive state machine has the following states:
Hardware
Rx DMA
Current Rx Desc Ptr
RxHead
link
bufptr
cmdsts
Rx Desc Cache
Rx Data FIFO
RXDP1
RXDP2
RXDP3
RXDP4
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