DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 41

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.2 Configuration and Media Status Register
This register allows configuration of a variety of device and phy options, and provides phy status information.
30-29
27-25
20-18
bit
31
28
24
23
22
21
17
4
3
2
1
0
SPDSTS[1:0] Speed Status
MODE_1000 1000 Mb/s Mode Control
PINT_CTL
TMRTEST
DUPSTS
LNKSTS
TBI_EN
TXR
RXD
RXE
TXD
TXE
tag
Offset: 0004h
(Continued)
Tag: CFG
Transmit Reset
Receiver Disable
Receiver Enable
Transmit Disable
Transmit Enable
Link Status
Full Duplex Status
Reserved
Ten-Bit Interface Enable
Reserved
Reserved
Phy Interrupt Control
Timer Test Mode
description
Access: Read Write
When set to a 1, this bit causes the current transmission to be aborted, the
transmit data and status FIFOs to be flushed, and the transmit state
machine to enter the idle state (TXE goes to 0). This is a write-only bit and
is always read back as 0.
Disable the receive state machine after any current packets in progress.
When this operation has been completed the RXE bit will be cleared to 0.
This is a write-only bit and is always read back as 0. If both RXD and RXE
are set in the same write, the RXE will be ignored, and RXD will have
precedence.
When set to a 1, and the receive state machine is idle, then the receive
machine becomes active. This bit will read back as a 1 whenever the
receive state machine is active. After initial power-up, software must insure
that the receiver has completely reset before setting this bit (See
ISR:RXRCMP).
When set to a 1, halts the transmitter after the completion of the current
packet. This is a write-only bit and is always read back as 0. If both TXD
and TXE are set in the same write, the TXE will be ignored, and TXD will
have precedence.
When set to a 1, and the transmit state machine is idle, then the transmit
state machine becomes active. This bit will read back as a 1 whenever the
transmit state machine is active. After initial power-up, software must insure
that the transmitter has completely reset before setting this bit (See
ISR:TXRCMP).
Link status of the external phy. Asserted when link is good. RO
Speed status indication from the external phy. SPDSTS[1] indicates the
value of the SPEED1000 input pin. SPDSTS[0] indicates the value of the
SPEED100 input pin. The actual values will depend on the polarity of the
signalling from the physical layer device. RO
Full Duplex status from the physical layer device as indicated by the
GP1DUP input pin. Asserted when duplex mode is set or has negotiated to
FULL. De-asserted when duplex mode has been set or negotiated to HALF.
When GP1_OE is set, this shows the status of the GP1_DUP output. RO
Reserved. RO
This bit enables the Ten-Bit Interface for use with 1000 Mb/s fiber devices.
When this bit is set, the MODE_1000 bit should also be set. It is loaded
from EEPROM at power-up. R/W
Reserved. Must be written as 0. R/W
This bit will enable 1000 Mb/s mode when set. This bit is loaded from
EEPROM at power-up. R/W
Reserved. Must be written as 0. R/W
Allows phy interrupt on changes in Phy status as follows:
Note that the phy interrupt mask in the IMR register must also be set.
Speeds up 100us internal timer signal to 4us.
Size: 32 bits
1xx: change in DUPSTS
x1x: change in LNKSTS
xx1: change in SPDSTS
41
usage
Hard Reset: 00000000h
Soft Reset: 00000000h
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