DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 47

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.7 Interrupt Mask Register
This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding
interrupt. During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to
cause an interrupt. ISR bits are always set to 1, however, if the condition is present, regardless of the state of the
corresponding mask bit.
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXDESC3
RXDESC2
RXDESC1
RXDESC0
TXDESC3
TXDESC2
TXDESC1
TXDESC0
RXEARLY
RXRCMP
TXRCMP
RXSOVR
RXDESC
TXDESC
RXORN
RXIDLE
DPERR
SSERR
RMABT
TXURN
TXIDLE
RXERR
HIBINT
TXERR
RTABT
RXOK
TXOK
PME
PHY
SWI
MIB
tag
Offset: 0014h
(Continued)
Tag: IMR
Tx Descriptor for Priority
Queue 3
Tx Descriptor for Priority
Queue 2
Tx Descriptor for Priority
Queue 1
Tx Descriptor for Priority
Queue 0
Rx Descriptor for Priority
Queue 3
Rx Descriptor for Priority
Queue 2
Rx Descriptor for Priority
Queue 1
Rx Descriptor for Priority
Queue 0
Transmit Reset Complete
Receive Reset Complete
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Rx Status FIFO Overrun
High Bits Interrupt
Phy interrupt
Power Management Event
Software Interrupt
MIB Service
Tx Underrun
Tx Idle
Tx Packet Error
Tx Descriptor
Tx Packet OK
Rx Overrun
Rx Idle
Rx Early Threshold
Rx Packet Error
Rx Descriptor
Rx OK
description
unused
When this bit is 3, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 2, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 1, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 3, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 2, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 1, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
Access: Read Write
Size: 32 bits
47
usage
Hard Reset: 00000000h
Soft Reset: 00000000h
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