DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 55

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.18.1 Wake on LAN
The Wake on LAN logic provides several mechanisms for
bringing the DP83820 out of a low-power state. Wake on
ARP , Wake on Broadcast, Wake on Multicast Hash and
Wake on Phy Interrupt are enabled by setting the
corresponding bit in the Wake Command/Status Register,
WCSR. Before the hardware is programmed to a low power
state, the software must write a null receive descriptor
pointer to the Receive Descriptor Pointer Register (RXDP)
to ensure wake packets will be buffered in the RX fifo.
Please refer to the description of the RXDP register for this
procedure.
When a qualifying packet is received, the Wake on LAN
logic generates a Wake event and asserts the PMEN PCI
signal to request a Power Management state change. The
software must then bring the hardware out of low power
mode and, if the Power Management state was D3,
reinitialize Configuration Register space. A Wake interrupt
can also be generated which alerts the software that a
Wake event has occurred and a packet was received. The
software must then write a valid receive descriptor pointer
4.2.19 Pause Control/Status Register
The PCR register is used to control and monitor the DP83820 Pause Frame reception and transmission. The Pause
Frame reception Logic is used to accept 802.3x Pause Frames, extract the pause length value, and initiate a TX MAC
pause interval of the specified number of slot times. The Pause Frame transmission logic is used to generate and
transmit Pause Frames to cause the far-end station to pause. Pause frames can be sent by manual control or by
programmed thresholds for the RX Data and Status FIFOs. The thresholds provide a flexible method of issuing initial
pause frames based on available space falling below the thresholds, as well as sending pause frames to cancel an active
pause interval when available space rises above the upper thresholds. Note that the thresholds are based on space
available in the FIFOs rather than space used. The transmitted Pause Frame is a Mac Control frame which contains the
following data:
bit
31
30
29
28
27
DA (destination address): Pause multicast address of 01-80-C2-00-00-01
SA (source address): Set to station’s address as specified in Receive Filter Perfect Match Register
Length/Type: Mac Control Frame Type (88-08)
Mac Control Opcode: Pause frame (00-01)
Pause Length field: Programmable in PAUSE_CNT when PLEN_SEL=0.
PS_MCAST
PS_RCVD
PS_ACT
PS_DA
PSEN
tag
Offset: 0044h
(Continued)
Tag: PCR
Pause Enable
Pause on Multicast
Pause on DA
Pause Active
Pause Frame Received
description
Access: Read Write
Manually enables reception of 802.3x pause frames This bit is ORed with
the PSNEG bit to enable pause reception. If pause reception has been
enabled via PSEN bit (PSEN=1), setting this bit to 0 will cause any active
pause interval to be terminated. R/W
When set to 1, this bit enables reception of 802.3x pause frames which use
the 802.3x designated multicast address in the DA (01-80-C2-00-00-01).
When this mode is enabled, the RX filter logic performs a perfect match on
the above multicast address. The pause frame will be filtered out (not
buffered to memory) unless the RX Filter logic is also programmed to
accept this address. R/W
When set to 1, this bit enables detection of a pause frame based on a DA
match with either the perfect match register, or one of the pattern match
buffers. R/W
This bit is set to a 1 when the TX MAC logic is actively timing a pause
interval. RO
This bit is set to a 1 when a pause frame has been received. This bit will
remain set until cleared by a read of this register. RO, cleared on read.
Size: 32 bits
55
to RXDP . The incoming packet can then be transferred into
host memory for processing. Note that the wake packet is
retained for processing - this is a feature of the DP83820.
In addition to the above Wake on LAN features, DP83820
also provides Wake on Pattern Matching, Wake on DA
match and Wake on Magic Packet with SecureOn.
4.2.18.2 Wake on Pattern Matching
Wake on Pattern Matching is an extension of the Pattern
Matching feature provided by the Receive Filter Logic.
When one or more of the Wake on Pattern Match bits are
set in the WCSR, a packet will generate a wake event if it
matches the associated pattern buffer. The pattern count
and the pattern buffer memory are accessed in the same
way as in Pattern Matching for packet acceptance. The
minimum pattern count is 2 bytes and the maximum
pattern count is128 bytes for all patterns. Packets are
compared on a byte by byte basis and bytes may be
masked in pattern memory, thus allowing for don’t cares.
Please refer to the Receive Filter section for programming
examples
usage
Hard Reset: 00000000h
Soft Reset: 00000000h
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