AD9911BCPZ Analog Devices Inc, AD9911BCPZ Datasheet - Page 10

• Manufacturer Part Number: AD9911BCPZ
• Description: IC DDS 500MSPS DAC 10BIT 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9911BCPZ

• Resolution (bits): 10 b
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Transmitting Current: 73mA
• Data Rate: 800Mbps
• Rf Ic Case Style: LFCSP
• No. Of Pins: 56
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9911/PCBZ - BOARD EVAL FOR AD9911AD9911/PCB - BOARD EVAL FOR AD9911
• Lead Free Status / Rohs Status: Compliant

AD9911
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5, 7, 8, 9, 11, 13, 14,
15, 19, 21, 26, 29,
30, 31, 33, 37, 39
18, 20, 25, 34, 38
45, 55
44, 56
35
36
17
22
23
24
27
Mnemonic
SYNC_IN
SYNC_OUT
MASTER_RESET
PWR_DWN_CTL
AVDD
AGND
DVDD
DGND
IOUT
IOUT
DAC_RSET
REF_CLK
REF_CLK
CLK_MODE_SEL
LOOP_FILTER
MASTER_RESET
PWR_DWN_CTL
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
SYNC_OUT
I/O
I
O
I
I
I
I
I
I
O
O
I
I
I
I
I
SYNC_IN
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
NC
NC
NC
Description
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_OUT pin of the master
AD9911 device.
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_IN pin of the slave
AD9911 device.
Active High Reset Pin. Asserting this pin forces the internal registers to the default
state shown in the Register Map section.
External Power-Down Control. See the Power Down Functions section for details.
Analog Power Supply Pins (1.8 V).
Analog Ground Pins.
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
Complementary DAC Output. Terminates into AVDD.
True DAC Output. Terminates into AVDD.
Establishes the Reference Current for the DAC. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in
single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
Reference Clock/Oscillator Input. When the REF_CLK operates in single-ended mode,
Pin 23 is the input. See the Modes of Operation section for the reference clock
configuration.
Control Pin for the Oscillator. CAUTION: Do not drive this pin beyond 1.8 V. When high
(1.8 V), the oscillator is enabled to accept a crystal as the REF_CLK source. When low,
the oscillator is bypassed.
Connects to the External Zero Compensation Network of the PLL Loop Filter. Typically,
the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Figure 6. Pin Configuration
Rev. 0 | Page 10 of 44
PIN 1
INDICATOR
NC = NO CONNECT
(Not to Scale)
TOP VIEW
AD9911
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2
P1
P0
AVDD
AGND
AVDD
IOUT
IOUT
AGND
AVDD
NC
AVDD
AVDD
AVDD