STSMIA832TBR STMicroelectronics, STSMIA832TBR Datasheet
STSMIA832TBR
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STSMIA832TBR Summary of contents
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V / 2.8 V high speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Features ■ Sub-low voltage differential signaling inputs 100 mV min. with ■ High signaling rate ...
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Contents Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STSMIA832 1 Schematic diagram Figure 1. Simplified application block diagram Figure 2. Block diagram Doc ID 12174 Rev 5 Schematic diagram 3/25 ...
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Pin configuration 2 Pin configuration Figure 3. Pin connections (top through view - bumps are on the other side) Table 1. Pin description Pin n° Symbol ...
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STSMIA832 2.1 Pin descriptions for reference: (D+, D-, STRB+, STRB-) Differential subLVDS data and strobe inputs to the receiver from the camera sensor interface. The signals operate at 150 mV typical differential voltage levels and a common mode voltage of ...
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Pin configuration Both the camera sensor module and the baseband processor interface operate 1.8 V. The subLVDS receiver core operating voltage 2.2 Supplementary notes: SMIA specification The standard mobile ...
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STSMIA832 Figure 5. Data-strobe signaling Data is sent byte-wise LSB first. The state of the data and strobe signals at the beginning of transmission are fixed i.e. the state of data is logic high and the state of strobe is ...
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Pin configuration In the beginning of frame and in the end of frame, line synchronization codes are replaced by the frame synchronization codes. Synchronization signal usage is shown in figure 7 below. Bit order of the synchronization codes is the ...
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STSMIA832 3 Application information 3.1 Inputs Technological advancements in deeper submicron processes have lowered the supply voltage levels of semiconductor devices, creating a design environment where system board devices may potentially use many different supply voltages, which can ultimately lead ...
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Application information 3.3 Power saving at the inputs All internal blocks of the input circuitry are shutdown by turning off the bias currents for the subLVDS receivers. This eliminates the power associated with any dynamic activity on the input pins. ...
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STSMIA832 Figure 9. STSMIA832 load capacitance and rise and fall time of LVTTL parallel outputs 3.7 Board layout To obtain the maximum benefit from the noise and EMI reductions of subLVDS, attention should be paid to the layout of differential ...
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Application information Figure 10. Bypass decoupling capacitors Table 3. Synchronization codes as per SMIA specifications Input EN SYNC_SEL SOF ( EOF( SOL( EOL( ...
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STSMIA832 4 Maximum ratings Table 5. Absolute maximum ratings Symbol V Main supply voltage DD V Secondary supply voltage L V SubLVDS data bus input voltage (D+, D SubLVDS clock bus input voltage (STRB+, STRB-) STRB V DC ...
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Electrical characteristics 5 Electrical characteristics Over recommended operating conditions unless otherwise noted. All typical values are °C, and V A Table 7. Electrical characteristics Symbol Parameter V Common mode input voltage CM V Receiver input low ...
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STSMIA832 Over recommended operating conditions unless otherwise noted. Typical values are referred °C and V A Table 9. Switching characteristics Symbol Parameter Rise time LVTTL output voltage t r (10% to 90%) Fall time LVTTL output ...
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Electrical characteristics Table 9. Switching characteristics (continued) Symbol Parameter Enable delay time t EN (EN to V-SYNC, H-SYNC) Disable delay time t DIS (EN to V-SYNC, H-SYNC) DR Max usable data rate MAX T Strobe target period STRB Minimum Data/Strobe ...
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STSMIA832 6 Frame structure Figure 11. Frame structure in VGA case (allowed synchronization codes sequence) Figure 12. Bit order in synchronization codes and data, LSB first (example start of frame), image frame structure Note: LSB (bytewise least significant bit first). ...
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Timing diagram 7 Timing diagram Unless otherwise specified T Figure 13. Disabled sync mode (SYNC_SEL = GND) (D1-D8 will transmit the input data DIN, including SYNC CODE) and CLASS_SEL = V Note: DATA_IN and STROBE are the input signals, CLKH ...
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STSMIA832 Figure 14. Enabled sync mode (SYNC_SEL = VDD) (D1-D8 will transmit the input data DIN, excluding SYNC CODE) and CLASS_SEL = V Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal extracted clock ...
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Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
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STSMIA832 Dim. Min 0.78 b 0. TFBGA25 mechanical data mm. Typ. Max. 1.1 1.16 0.25 0.86 0.30 0.35 3.0 3.1 2 3.0 3.1 2 0.5 0.25 Doc ID ...
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Package mechanical data Tape & reel TFBGA25 mechanical data Dim. Min 12 3.9 P 7.9 22/25 mm. Typ. Max. Min. 330 13.2 0.504 0.795 2.362 14.4 3.3 3.3 1.60 ...
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... STSMIA832 9 Order code Table 10. Order code Temperature Order code range STSMIA832TBR - °C Package TFBGA25 (tape and reel) Doc ID 12174 Rev 5 Order code Packaging 3000 parts per reel 23/25 ...
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Revision history 10 Revision history Table 11. Document revision history Date Revision 13-Mar-2006 1 3-May-2006 2 03-Jun-2009 3 28-Sep-2009 4 13-May-2010 5 24/25 Initial release. Modified table 3 - output. Modified Figure 9 on page 11. Added row ESD Table ...
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... STSMIA832 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...