CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 13

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

3.7.2
3.7.2.1 FIFOADDR Lines
The SX2 has three address pins that are used to select either the FIFOs or the command interface. The addresses correspond
to the following table.
Table 3-3. FIFO Address Lines Setting
The SX2 accepts either an internally derived clock (30 or 48 MHz) or externally supplied clock (IFCLK, 5-50 MHz), and SLRD,
SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals from an external master. The interface can be selected for 8- or 16- bit
operation by an internal configuration bit, and an Output Enable signal SLOE enables the data bus driver of the selected width.
The external master must ensure that the output enable signal is inactive when writing data to the SX2. The interface can operate
either asynchronously where the SLRD and SLWR signals act directly as strobes, or synchronously where the SLRD and SLWR
act as clock qualifiers. The optional CS# signal will tristate the data bus and ignore SLRD, SLWR, PKTEND.
The external master reads from OUT endpoints and writes to IN endpoints, and reads from or writes to the command interface.
3.7.2.2 Read: SLOE and SLRD
In synchronous mode, the FIFO pointer is incremented on each rising edge of IFCLK while SLRD is asserted. In asynchronous
mode, the FIFO pointer is incremented on each asserted-to-deasserted transition of SLRD.
SLOE is a data bus driver enable. When SLOE is asserted, the data bus is driven by the SX2.
3.7.2.3 Write: SLWR
In synchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising edge of
IFCLK while SLWR is asserted. In asynchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is
incremented) on each asserted-to-deasserted transition of SLWR.
3.7.2.4 PKTEND
PKTEND commits the current buffer to USB. To send a short IN packet (one which has not been filled to max packet size
determined by the value of PL[X:0] in EPxPKTLENH/L), the external master strobes the PKTEND pin.
3.7.3
The IFCLK pin can be configured to be either an input (default) or an output interface clock. Bits IFCONFIG[7:4] define the
behavior of the interface clock. To use the SX2’s internally-derived 30- or 48-MHz clock, set IFCONFIG.7 to 1 and set IFCONFIG.6
to 0 (30 MHz) or to 1 (48 MHz). To use an externally supplied clock, set IFCONFIG.7=0 and drive the IFCLK pin (5 MHz – 50
MHz). The input or output IFCLK signal can be inverted by setting IFCONFIG.4=1.
3.7.4
An external master can access the slave FIFOs either asynchronously or synchronously:
An external master accesses the FIFOs through the data bus, FD [15:0]. This bus can be either 8- or 16-bits wide; the width is
selected via the WORDWIDE bit in the EPxPKTLENH/L registers. The data bus is bidirectional, with its output drivers controlled
by the SLOE pin. The FIFOADR[2:0] pins select which of the four FIFOs is connected to the FD [15:0] bus, or if the command
interface is selected.
Document #: 38-08013 Rev. *B
• Asynchronous–SLRD, SLWR, and PKTEND pins are strobes.
• Synchronous–SLRD, SLWR, and PKTEND pins are enables for the IFCLK clock pin.
Control Signals
IFCLK
FIFO Access
Address/Selection
RESERVED
RESERVED
RESERVED
COMMAND
FIFO2
FIFO4
FIFO6
FIFO8
FIFOADR2
0
0
0
0
1
1
1
1
FIFOADR1
0
0
1
1
0
0
1
1
CY7C68001
FIFOADR0
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0
1
0
1
0
1
0
1