CYP15G0101DXB-BBXC Cypress Semiconductor Corp, CYP15G0101DXB-BBXC Datasheet - Page 14

• Manufacturer Part Number: CYP15G0101DXB-BBXC
• Description: IC TXRX HOTLINK 100-LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0101DXB-BBXC

• Package / Case: 100-LBGA
• Protocol: Fibre Channel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.5 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0101DX-EVAL - EVAL BRD FOR HOTLINK II
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2920; CYP15G0101DXB-BBXC

Document #: 38-02031 Rev. *J
When parity checking is enabled and TXMODE[1] = HIGH, all
characters (including those in the middle of a Word Sync
Sequence) must have correct parity. The detection of a
character with incorrect parity during a Word Sync Sequence
(regardless of the state of TXCT[1:0]) will interrupt that
sequence and force generation of a C0.7 SVS character. Any
interruption of the Word Sync Sequence causes the sequence
to terminate.
When TXCKSEL = LOW, the Input Register for the transmit
channel is clocked by REFCLK.
MID, the Input Register for the transmit channel is clocked with
TXCLK↑.
TX Mode 4—Atomic Word Sync and SCSEL Control of
Word Sync Sequence Generation
When configured in TX Mode 4, the SCSEL input is captured
along with the TXCT[1:0] data control inputs. These bits
combine to control the interpretation of the TXD[7:0] bits and
the characters generated by them. These bits are interpreted
as listed in Table 6.
Table 6. TX Modes 4 and 7 Encoding
TX Mode 4 also supports an Atomic Word Sync Sequence.
Unlike TX Mode 3, this sequence is started when both SCSEL
and TXCT[0] are sampled HIGH. With the exception of the
combination of control bits used to initiate the sequence, the
generation and operation of this Word Sync Sequence is the
same as that documented for TX Mode 3.
TX Mode 5—Atomic Word Sync, No SCSEL
When configured in TX Mode 5, the SCSEL signal is not used.
The TXCT[1:0] inputs control the characters generated by the
channel. The specific characters generated by these bits are
listed in Table 7.
Table 7. TX Modes 5 and 8 Encoding
TX Mode 5 also has the capability of generating an Atomic
Word Sync Sequence. For the sequence to be started, the
TXCT[1:0] inputs must both be sampled HIGH. The generation
and operation of this Word Sync Sequence is the same as that
documented for TX Mode 3.
X
X
X
X
X
0
0
1
X
X
0
1
0
0
1
1
0 Encoded data character
1 K28.5 fill character
1 Special character code
1 16-character Word Sync Sequence
0 Encoded data character
1 K28.5 fill character
0 Special character code
1 16-character Word Sync Sequence
Characters Generated
Characters Generated
[3]
When TXCKSEL = HIGH or
Transmit BIST
The transmit channel contains an internal pattern generator
that can be used to validate both device and link operation.
This generator is enabled by the BOE[1] signal, as listed in
Table 8 (when the BISTLE latch enable input is HIGH). When
enabled, a register in the transmit channel becomes a
signature pattern generator by logically converting to a Linear
Feedback Shift Register (LFSR). This LFSR generates a
511-character sequence that includes all Data and Special
Character codes, including the explicit violation symbols. This
provides a predictable yet pseudo-random sequence that can
be matched to an identical LFSR in the attached Receiver. If
the receive channel is configured for REFCLK clocking
(RXCKSEL = LOW), each pass is preceded by a 16-character
Word Sync Sequence to allow Elasticity Buffer alignment and
management of clock-frequency variations.
When the BISTLE signal is HIGH, if the BOE[1] input is LOW,
the BIST generator in the transmit channel is enabled (and if
BOE[0] = LOW the BIST checker in the receive channel is
enabled). When BISTLE returns LOW, the values of the
BOE[1:0] signals are captured in the BIST Enable Latch.
These values remain in the BIST Enable Latch until BISTLE is
returned high to open the latch again. A device reset (TRSTZ
sampled LOW), also presets the BIST Enable Latch to disable
BIST on both the transmit and receive channels.
All data and data-control information present at the TXD[7:0]
and TXCT[1:0] inputs are ignored when BIST is active on the
transmit channel.
Serial Output Drivers
The serial interface Output Drivers use high-performance
differential
source-matched drivers for the transmission lines. These
Serial Drivers accept data from the Transmit Shifter. These
outputs have signal swings equivalent to that of standard
PECL drivers, and are capable of driving AC-coupled optical
modules or AC-coupled transmission lines. To acheive OBSAI
RP3 compliancy, the serial output drivers must be AC-coupled
to the transmission medium.
When configured for local loop-back (LPEN = HIGH), the
enabled Serial Drivers are configured to drive a static differ-
ential logic-1.
Each Serial Driver can be enabled or disabled through the
BOE[1:0] inputs, as controlled by the OELE latch-enable
signal. When OELE = HIGH, the signals present on the
BOE[1:0] inputs are passed through the Serial Output Enable
latch to control the Serial Driver. The BOE[1:0] input with
OUT1± and OUT2± driver is listed in Table 8.
Table 8. Output Enable, BIST, and Receive Channel
Enable Signal Map
When OELE = HIGH and BOE[x] = HIGH, the associated
Serial Driver is enabled to drive any attached transmission
line. When OELE = HIGH and BOE[x] = LOW, the associated
driver is disabled and internally configured for minimum power
BOE[1]
BOE[0]
Input
BOE
Current
Controlled
(OELE)
Output
OUT2±
OUT1±
Mode
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
Logic
(BISTLE)
Channel
Transmit
Receive
Enable
BIST
(CML)
Page 14 of 39
Receive PLL
to
Channel
Receive
Enable
(RXLE)
X
provide
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