CYP15G0101DXB-BBXC Cypress Semiconductor Corp, CYP15G0101DXB-BBXC Datasheet

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... CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices. ...

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... CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices. ...

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... RFMODE DECMODE RXRATE RXMODE RXCKSEL Document Number: 38-02031 Rev. *L Bit-Rate Clock Transmit Mode BIST Enable Latch Clock Select Boundary Controller CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB = Internal Signal TRSTZ Character-Rate Clock 10 OUT1+ OUT1– OUT2+ OUT2– TXLB 2 Output Enable OELE Latch BISTLE LFI ...

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... Power Control ............................................................ 20 Output Bus ................................................................ 21 Parity Generation ...................................................... 22 JTAG Support ............................................................ 23 Maximum Ratings ........................................................... 25 Power-up Requirements ............................................ 25 DC Electrical Characteristics ........................................ 25 Document Number: 38-02031 Rev. *L CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB AC Test Loads and Waveforms ..................................... 26 CYP(V)(W)15G0101DXB AC Characteristics ................ 27 Switching Waveforms for the HOTLink II Transmitter 29 X3.230 Codes and Notation Conventions .................... 33 Notation Conventions ................................................ 33 8B/10B Transmission Code ...

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... SDASEL RXRATE RXCLKC+ GND GND GND GND GND GND GND GND GND GND GND GND TXD[6] TXCT[1] LFI TXD[5] TXCT[0] RXCLK– TXD[4] TXD[7] RXCLK+ CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB IN1+ V OUT1– [3] IN1– #NC OUT1+ V SPDSEL PARCTL RFMODE INSEL GND TMS TRSTZ ...

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... Note 4. When REFCLK is configured for half-rate operation (TXRATE REFCLK. Document Number: 38-02031 Rev. *L Table 1 for details. Table 1 for details. Table 2 = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB for details. Page [+] Feedback ...

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... Table 9 for a list of operating serial rates. Table 3 for a list of operating modes. = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of (ground). The HIGH level is usually implemented by direct connection CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB ). TXLOCK [5] (power). When not CC Page ...

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... Document Number: 38-02031 Rev. *L Table 13 for details. Table 16 for a list of receive character status. th the serial bit-rate) of the data being received, as selected by = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB th the serial Page [+] Feedback ...

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... MID level. Document Number: 38-02031 Rev. *L for details. Table 2 and Table 15 for details. (ground). The HIGH level is usually implemented by direct connection CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 21 for a list of the (power). When not CC Page [+] Feedback ...

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... They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH. The LOW level is usually implemented by direct connection to V connected or allowed to float, a 3-level select input will self-bias to the MID level. Document Number: 38-02031 Rev. *L Table (ground). The HIGH level is usually implemented by direct connection CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB 10. (power). When not CC Page ...

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... V power CC GND Signal and power ground for all internal circuits. Document Number: 38-02031 Rev. *L 14. When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 14. If the device is Table 14. When the latch is closed, if the ...

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... ODD parity along with the TXOP bit. When PARCTL = HIGH with the encoder enabled (or MID with the encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are checked for ODD parity along with the TXOP bit. When PARCTL = LOW, parity checking is disabled. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB to REFCLK ...

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... SCSEL, TXCT[1], and TXCT[0] that are used to control the generation of data and control characters. These multiple encoding forms allow maximum flexibility in interfacing to legacy applications, while also supporting numerous extensions in capabilities.TX Mode 0—encoder bypass CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 21. When directed to encode the Table 20 ...

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... TXD[7:0] bits do not directly control the generation of characters during the Word Sync h Sequence. Once the sequence is started, parity is not checked j on the following 15 characters in the Word Sync Sequence. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Characters Generated Encoded data character K28.5 fill character ...

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... All data and data-control information present at the TXD[7:0] and TXCT[1:0] inputs are ignored when BIST is active on the transmit channel. = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Characters Generated Table 8 Page ...

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... Each receiver provides internal DC-restoration, to the center of the receiver’s common mode range, for AC-coupled and 154 MHz for signals. = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB [16] (ternary) input that selects one of Table 9. REFCLK ...

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... When RXLE returns LOW, the values present on the BOE[1:0] inputs are latched in the Receive Channel Enable Latch, and remain there until RXLE returns HIGH to open the [20] latch again. = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB [17] as Table 8. ...

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... When operated with a half-character-rate output clock (RXRATE = HIGH), the output of properly framed characters may be delayed character-clock cycles from the detection of the selected framing [23] character. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB allows selection of two ...

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... The specific patterns checked by each receiver are described in detail in the Cypress application note The sequence compared by the CYP(V)(W)15G0101DXB is identical to that in the CY7B933 and CY7C924DX, allowing interoperable systems to be built when used at compatible serial signaling rates. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 20 and Table 21 ...

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... Prior to reception of valid data, at least one Word Sync Sequence (or at least four framing characters) must be received to allow the Document Number: 38-02031 Rev. *L CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB receive elasticity buffer to be centered. The elasticity buffer may also be centered by a device reset operation initiated through the TRSTZ input ...

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... RXD[6] enabled (RFEN = HIGH). When the framer is disabled, the clock boundaries are not adjusted, and COMDET may be asserted RXD[7] during the rising edge of RXCLK– (if an odd number of characters were received following the initial framing). CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 14. Bus Weight ...

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... X To ensure compatibility between the source and destination systems when operating in BIST, the sending and receiving ends of the BIST sequence must use the same clock setup (RXCKSEL = MID or RXCKSEL = LOW). = LOW. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 16. and Table 16. When the receive PLL detects ...

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... Each 3-level select input reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11, respectively. Description Type-B Status Table buffer RESERVED or framing CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Receive BIST Status (Receive BIST = Enabled) BIST data compare. 20. Character compared correctly BIST command compare ...

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... BIST_START (101) Elasticity Buffer Error Yes No Compare Next Character RXST = BIST_COMMAND_COMPARE (001) Match Command Data or Command Data End-of-BIST No State Yes, RXST = BIST_LAST_GOOD (010) No, RXST = BIST_ERROR (110) CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Receive BIST Detected LOW RX PLL Out of Lock RXST = BIST_DATA_COMPARE (000) Page [+] Feedback ...

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... Min  V  Max CC Min  V  Max CC Min  V  Max GND IN 100  differential load 150  differential load CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB °C to +70 °C +3.3 V ±5% +3.3 V ±5% Min Max Unit 2 0.4 V –20 –100 mA –20 20 µA 2 ...

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... V th  270 ps (d) CML/LVPECL Input Test Waveform  [36] requirement still needs to be satisfied. DIFFS = = 3.3V, T 25°C, parallel outputs unloaded, RXCKSEL CC A CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Min Max Unit 1.4 0 1.4 0.7 ...

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... The duty cycle specification is a simultaneous condition with the t cannot be as large as 30%–70%. Document Number: 38-02031 Rev. *L Description and t parameters. This means that at faster character rates the REFCLK duty cycle REFH REFL CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Min Max Unit [37] 19.5 150 ...

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... IEEE 802.3z IEEE 802.3z Test Conditions ° °  = 12. Hence: Total Jitter ( 14 10) (when RXRATE = LOW data is being received, or 1/(f REF CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Min Max Unit – 9.5 ns 2.5 – ns 10UI – 4.7 – ns 0.5 – ns 10UI – 4.3 – ns – ...

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... Document Number: 38-02031 Rev TXCLK t TXCLKL t TXDS t TXDH t REFCLK t REFL t TREFDS t TREFDH t REFCLK t REFH Note 53 t TREFDS t TREFDH t REFCLK t REFH t TXCLKO t TXCLKOD– 54 Note = HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB t REFL t TREFDS t REFL = LOW), data Page [+] Feedback ...

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... Document Number: 38-02031 Rev REFCLK t REFL 54 Note t TXCLKO t TXCLKOD– t REFCLK t REFL t t RREFDV RREFDA t REFDV+ t REFCDV+ 57 Note t REFCLK t REFH t RREFDA t t RREFDV RREFDV t REFDV+ t REFCDV+ 57 Note CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB t REFDV– t REFCDV– t REFL t RREFDA t REFDV– t REFCDV– 58 Note Page [+] Feedback ...

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... RXRATE = LOW RXCLK+ – RXCLK RXD[7:0], RXST[2:0], RXOP Receive Interface Read Timing RXCKSEL = MID RXRATE = HIGH RXCLK+ – RXCLK RXD[7:0], RXST[2:0], RXOP Document Number: 38-02031 Rev RXCLKP t RXCLKL t RXDV– t RXDV+ t RXCLKP t RXCLKH t RXDV– t RXDV+ CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB t RXCLKL Page [+] Feedback ...

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... RXD[1] LVTTL OUT G3 RXD[5] LVTTL OUT G4 GND GROUND G5 GND GROUND G6 GND GROUND G7 GND GROUND G8 TXOP LVTTL IN PU CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Ball Signal Name Signal Type ID G9 TXCLKO+ LVTTL OUT G10 TXCLKO– LVTTL OUT H1 RXD[0] LVTTL OUT H2 RXD[2] LVTTL OUT H3 RXD[6] ...

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... Transmission Character is a Data Character (c is set to D, and SC/D = LOW Special Character (c is set to K, and SC/D = HIGH). When Document Number: 38-02031 Rev. *L CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB c is set the decimal value of the binary number ...

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... Transmission Character in which the error occurred. Table 19 Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 18 Data OUT Hex Value 765 43210 000 00000 00 000 00001 01 ...

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... D31.1 001 11111 011000 0101 D0.3 011 00000 100010 0101 D1.3 011 00001 010010 0101 D2.3 011 00010 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 ...

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... D3.5 101 00011 001010 1101 D4.5 101 00100 101001 0010 D5.5 101 00101 011001 0010 D6.5 101 00110 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD Current RD+ abcdei fghj abcdei fghj 110001 1100 110001 0011 110101 0011 001010 1100 101001 1100 101001 0011 ...

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... D7.7 111 00111 000110 0110 D8.7 111 01000 100101 0110 D9.7 111 01001 010101 0110 D10.7 111 01010 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD Current RD+ abcdei fghj abcdei fghj 111000 1010 000111 1010 111001 1010 000110 1010 100101 1010 100101 1010 ...

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... D28.7 111 11100 010001 0110 D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD Current RD+ abcdei fghj abcdei fghj 110100 1110 110100 1000 001101 1110 001101 0001 101100 1110 101100 1000 ...

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... C1.7 (CE1) 111 00001 [70] C2.7 (CE2) 111 00010 [70] C4.7 (CE4) 111 00100 the specified value between 00 and FF). = HIGH. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB [59,60] Current RD Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 ...

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... Ordering Information Speed Ordering Code Standard CYP15G0101DXB-BBC Standard CYP15G0101DXB-BBI Standard CYV15G0101DXB-BBI Standard CYP15G0101DXB-BBXC Standard CYP15G0101DXB-BBXI Standard CYV15G0101DXB-BBXC OBSAI CYW15G0101DXB-BBXI Ordering Code Definitions CY X15G0101 X DXB - BB X Document Number: 38-02031 Rev. *L Package Name Package Type BB100 100-ball Grid Array BB100 100-ball Grid Array ...

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... Package Diagram Figure 3. 100-ball Thin Ball Grid Array ( 1.4 mm) BB100 Document Number: 38-02031 Rev. *L CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB 51-85107 *C Page [+] Feedback ...

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... JTAG joint test action group PLL phase-locked loop TMS test mode select TDO test data out TDI test data in Document Number: 38-02031 Rev. *L CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Units of Measure Acronym Description °C degree Celsius k Kilo ohm µA micro Amperes µs ...

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... Document History Page Document Title: CYP15G0101DXB/CYV15G0101DXB/CYW15G0101DXB Single-channel HOTLink II™ Transceiver Document Number: 38-02031 REV. ECN NO. Issue Date ** 113123 05/20/02 *A 119704 10/30/02 *B 122209 12/28/02 *C 122546 02/13/03 *D 124994 04/15/03 *E 128366 7/3/03 *F 128835 7/31/03 *G 131898 12/10/03 *H 211461 See ECN *I 230621 See ECN *J 338721 See ECN ...

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... Document Title: CYP15G0101DXB/CYV15G0101DXB/CYW15G0101DXB Single-channel HOTLink II™ Transceiver Document Number: 38-02031 REV. ECN NO. Issue Date *L 3053045 10/08/2010 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office ...