LAN8700C-AEZG SMSC, LAN8700C-AEZG Datasheet - Page 54

• Manufacturer Part Number: LAN8700C-AEZG
• Description: TXRX ETHERNET 10/100 36-QFN
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8700C-AEZG

• Protocol: MII, RMII
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3ab
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1046; 638-1046-1; 638-1046-1

Revision 2.2 (12-04-09)
5.4.9.2
MODE[2:0]
000
001
010
100
101
011
110
111
PHY application, this ensures that the scramblers are out of synchronization and disperses the
electromagnetic radiation across the frequency spectrum.
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin is
deasserted, the register bit values are loaded according to the MODE[2:0] pins. The 10/100 digital
block is then configured by the register bit values. When a soft reset occurs (bit 0.15) as described in
Table
MODE[2:0] pins have no affect.
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
100Base-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
Power Down mode. In this mode the PHY will
wake-up in Power-Down mode. The PHY cannot be
used when the MODE[2:0] bits are set to this mode.
To exit this mode, the MODE bits in Register 18.7:5
(see
value and a soft reset must be issued.
All capable. Auto-negotiation enabled.
5.30, the configuration of the 10/100 digital block is controlled by the register bit values, and the
Table
5.39) must be configured to some other
MODE DEFINITIONS
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Table 5.48 MODE[2:0] Bus
DATASHEET
54
DEFAULT REGISTER BIT VALUES
REGISTER 0
[13,12,10,8]
X10X
0000
0001
1000
1001
1100
1100
N/A
SMSC LAN8700/LAN8700i
®
REGISTER 4
Technology in a Small Footprint
[8,7,6,5]
0100
0100
1111
N/A
N/A
N/A
N/A
N/A
Datasheet