DSPIC30F5011-30I/PT Microchip Technology Inc., DSPIC30F5011-30I/PT Datasheet - Page 114
DSPIC30F5011-30I/PT
Manufacturer Part Number
DSPIC30F5011-30I/PT
Description
16 BIT MCU/DSP 64LD 30MIPS 66 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F5011-30IPT.pdf
(224 pages)
Specifications of DSPIC30F5011-30I/PT
A/d Inputs
16-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
66K Bytes
Ram Size
4K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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dsPIC30F5011/5013
17.5.6
Transmit interrupts can be divided into 2 major groups,
each including various conditions that generate
interrupts:
• Transmit Interrupt:
• Transmit Error Interrupts:
FIGURE 17-2:
DS70116F-page 112
T
- Transmitter Warning Interrupt:
- Transmitter Error Passive:
- Bus Off:
At least one of the three transmit buffers is empty
(not scheduled) and can be loaded to schedule a
message for transmission. Reading the TXnIF
flags will indicate which transmit buffer is available
and caused the interrupt.
A transmission error interrupt will be indicated by
the ERRIF flag. This flag shows that an error con-
dition occurred. The source of the error can be
determined by checking the error flags in the CAN
Interrupt Status register, CiINTF. The flags in this
register are related to receive and transmit errors.
Input Signal
Q
The TXWAR bit indicates that the transmit error
counter has reached the CPU warning limit of
96.
The TXEP bit (CiINTF<12>) indicates that the
transmit error counter has exceeded the error
passive limit of 127 and the module has gone to
error passive state.
The TXBO bit (CiINTF<13>) indicates that the
transmit error counter has exceeded 255 and
the module has gone to the bus off state.
TRANSMIT INTERRUPTS
Sync
CAN BIT TIMING
Segment
Prop
Segment 1
Phase
Sample Point
17.6
All nodes on any particular CAN bus must have the
same nominal bit rate. In order to set the baud rate, the
following parameters have to be initialized:
• Synchronization Jump Width
• Baud Rate Prescaler
• Phase Segments
• Length determination of Phase Segment 2
• Sample Point
• Propagation Segment bits
17.6.1
All controllers on the CAN bus must have the same
baud rate and bit length. However, different controllers
are not required to have the same master oscillator
clock. At different clock frequencies of the individual
controllers, the baud rate has to be adjusted by
adjusting the number of time quanta in each segment.
The nominal bit time can be thought of as being divided
into separate non-overlapping time segments. These
segments are shown in Figure 17-2.
• Synchronization Segment (Sync Seg)
• Propagation Time Segment (Prop Seg)
• Phase Segment 1 (Phase1 Seg)
• Phase Segment 2 (Phase2 Seg)
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
T
of 8 T
the minimum nominal bit time is 1 sec corresponding
to a maximum bit rate of 1 MHz.
Q
. By definition, the nominal bit time has a minimum
Q
and a maximum of 25 T
Baud Rate Setting
BIT TIMING
Segment 2
Phase
© 2006 Microchip Technology Inc.
Q
. Also, by definition,
Sync
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