DSPIC30F5011-30I/PT Microchip Technology Inc., DSPIC30F5011-30I/PT Datasheet - Page 218

• Manufacturer Part Number: DSPIC30F5011-30I/PT
• Description: 16 BIT MCU/DSP 64LD 30MIPS 66 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5011-30I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 4K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F5011/5013
Oscillator Start-up Timer
Output Compare Interrupts ................................................. 85
Output Compare Module..................................................... 83
Output Compare Operation During CPU Idle Mode............ 85
Output Compare Sleep Mode Operation............................. 85
P
Packaging Information ...................................................... 207
Peripheral Module Disable (PMD) Registers .................... 152
PICSTART Plus Development Programmer ..................... 166
Pinout Descriptions ............................................................. 10
PLL Clock Timing Specifications....................................... 178
POR. See Power-on Reset.
Port Write/Read Example.................................................... 60
PORTA
PORTB
PORTC
PORTD
PORTF
PORTG
Power Saving Modes ........................................................ 150
Power-Down Current (I
Power-up Timer
Program Address Space ..................................................... 23
Program and EEPROM Characteristics ............................ 175
Program Counter................................................................. 14
Programmable................................................................... 139
Programmer’s Model........................................................... 14
DS70116F-page 216
Timing Characteristics .............................................. 181
Timing Requirements ................................................ 182
Register Map............................................................... 86
Timing Characteristics .............................................. 187
Timing Requirements ................................................ 187
Marking ..................................................................... 207
Register Map for dsPIC30F5013 ................................ 61
Register Map for dsPIC30F5011/5013 ....................... 61
Register Map for dsPIC30F5011 ................................ 61
Register Map for dsPIC30F5013 ................................ 61
Register Map for dsPIC30F5011 ................................ 62
Register Map for dsPIC30F5013 ................................ 62
Register Map for dsPIC30F5011 ................................ 62
Register Map for dsPIC30F5013 ................................ 62
Register Map for dsPIC30F5011/5013 ....................... 62
Idle ............................................................................ 151
Sleep ......................................................................... 150
Sleep and Idle ........................................................... 139
Timing Characteristics .............................................. 181
Timing Requirements ................................................ 182
Construction ................................................................ 24
Data Access from Program Memory Using
Data Access From Program Memory Using
Data Access from, Address Generation...................... 24
Data Space Window into Operation ............................ 27
Data Table Access (LS Word) .................................... 25
Data Table Access (MS Byte) ..................................... 26
Memory Map ............................................................... 23
Table Instructions
Diagram ...................................................................... 15
Program Space Visibility ..................................... 26
Table Instructions................................................ 25
TBLRDH.............................................................. 25
TBLRDL .............................................................. 25
TBLWTH ............................................................. 25
TBLWTL.............................................................. 25
PD
) ................................................ 171
Programming Operations.................................................... 49
Protection Against Accidental Writes to OSCCON ........... 144
R
Reader Response............................................................. 220
Reset ........................................................................ 139, 145
Reset Sequence ................................................................. 43
Reset Sources
Reset Timing Characteristics............................................ 181
Reset Timing Requirements ............................................. 182
Run-Time Self-Programming (RTSP) ................................. 47
S
Simple Capture Event Mode............................................... 79
Simple OC/PWM Mode Timing Requirements ................. 188
Simple Output Compare Match Mode ................................ 84
Simple PWM Mode ............................................................. 84
Software Simulator (MPLAB SIM) .................................... 164
Software Stack Pointer, Frame Pointer .............................. 14
SPI Module ......................................................................... 87
Status Bits, Their Significance and the Initialization
Algorithm for Program Flash....................................... 49
Erasing a Row of Program Memory............................ 49
Initiating the Programming Sequence......................... 50
Loading Write Latches ................................................ 50
BOR, Programmable ................................................ 147
Brown-out Reset (BOR)............................................ 139
Oscillator Start-up Timer (OST) ................................ 139
POR
POR (Power-on Reset)............................................. 145
Power-on Reset (POR)............................................. 139
Power-up Timer (PWRT) .......................................... 139
Reset Sources ............................................................ 43
Brown-out Reset (BOR).............................................. 43
Illegal Instruction Trap ................................................ 43
Trap Lockout............................................................... 43
Uninitialized W Register Trap ..................................... 43
Watchdog Time-out .................................................... 43
Buffer Operation ......................................................... 80
Hall Sensor Mode ....................................................... 80
Prescaler .................................................................... 79
Timer2 and Timer3 Selection Mode............................ 80
Input Pin Fault Protection ........................................... 84
Period ......................................................................... 85
CALL Stack Frame ..................................................... 31
Framed SPI Support ................................................... 87
Operating Function Description .................................. 87
Operation During CPU Idle Mode ............................... 89
Operation During CPU Sleep Mode............................ 89
SDOx Disable ............................................................. 87
Slave Select Synchronization ..................................... 89
SPI1 Register Map...................................................... 90
SPI2 Register Map...................................................... 90
Timing Characteristics
Timing Requirements
Word and Byte Communication .................................. 87
Condition for RCON Register, Case 1 ...................... 148
Operating without FSCM and PWRT................ 147
With Long Crystal Start-up Time ...................... 147
Master Mode (CKE = 0).................................... 192
Master Mode (CKE = 1).................................... 193
Slave Mode (CKE = 1).............................. 194, 195
Master Mode (CKE = 0).................................... 192
Master Mode (CKE = 1).................................... 193
Slave Mode (CKE = 0)...................................... 194
Slave Mode (CKE = 1)...................................... 196
© 2006 Microchip Technology Inc.