DSPIC30F5011-30I/PT Microchip Technology Inc., DSPIC30F5011-30I/PT Datasheet - Page 216

• Manufacturer Part Number: DSPIC30F5011-30I/PT
• Description: 16 BIT MCU/DSP 64LD 30MIPS 66 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5011-30I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 4K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F5011/5013
D
Data Accumulators and Adder/Subtractor........................... 19
Data Address Space ........................................................... 27
Data Converter Interface (DCI) Module ............................ 119
Data EEPROM Memory ...................................................... 53
DC Characteristics ............................................................ 167
DCI Module
DS70116F-page 214
Data Space Write Saturation ...................................... 21
Overflow and Saturation ............................................. 19
Round Logic ................................................................ 20
Write Back................................................................... 20
Alignment .................................................................... 30
Alignment (Figure) ...................................................... 30
Effect of Invalid Memory Accesses (Table)................. 30
MCU and DSP (MAC Class) Instructions
Memory Map ......................................................... 27, 28
Near Data Space ........................................................ 31
Software Stack ............................................................ 31
Spaces ........................................................................ 30
Width ........................................................................... 30
Erasing ........................................................................ 54
Erasing, Block ............................................................. 54
Erasing, Word ............................................................. 54
Protection Against Spurious Write .............................. 57
Reading....................................................................... 53
Write Verify ................................................................. 57
Writing ......................................................................... 55
Writing, Block .............................................................. 56
Writing, Word .............................................................. 55
BOR .......................................................................... 175
Brown-out Reset ....................................................... 174
I/O Pin Output Specifications .................................... 173
Idle Current (I
Low-Voltage Detect................................................... 173
LVDL ......................................................................... 174
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 175
Temperature and Voltage Specifications .................. 168
Bit Clock Generator................................................... 123
Buffer Alignment with Data Frames .......................... 125
Buffer Control ............................................................ 119
Buffer Data Alignment ............................................... 119
Buffer Length Control ................................................ 125
COFS Pin .................................................................. 119
CSCK Pin .................................................................. 119
CSDI Pin ................................................................... 119
CSDO Mode Bit ........................................................ 126
CSDO Pin ................................................................. 119
Data Justification Control Bit ..................................... 124
Device Frequencies for Common Codec CSCK Frequen-
Digital Loopback Mode ............................................. 126
Enable ....................................................................... 121
Frame Sync Generator ............................................. 121
Frame Sync Mode Control Bits ................................. 121
I/O Pins ..................................................................... 119
Interrupts ................................................................... 126
Introduction ............................................................... 119
Master Frame Sync Operation .................................. 121
Operation .................................................................. 121
Operation During CPU Idle Mode ............................. 126
Operation During CPU Sleep Mode .......................... 126
Receive Slot Enable Bits........................................... 124
Example .............................................................. 29
cies (Table) ....................................................... 123
IDLE
) .................................................... 170
DD
)............................................. 169
PD
) ........................................ 171
Development Support ....................................................... 163
Device Configuration
Device Configuration Registers
Device Overview................................................................... 7
Disabling the UART .......................................................... 101
Divide Support .................................................................... 16
DSP Engine ........................................................................ 17
Dual Output Compare Match Mode .................................... 84
E
Electrical Characteristics .................................................. 167
Enabling and Setting Up UART
Enabling the UART ........................................................... 101
Equations
Errata .................................................................................... 6
Exception Sequence
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 177
External Interrupt Requests ................................................ 45
F
Fast Context Saving ........................................................... 45
Flash Program Memory ...................................................... 47
Receive Status Bits................................................... 125
Register Map ............................................................ 128
Sample Clock Edge Control Bit ................................ 124
Slave Frame Sync Operation.................................... 122
Slot Enable Bits Operation with Frame Sync............ 124
Slot Status Bits ......................................................... 126
Synchronous Data Transfers .................................... 124
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 124
Transmit Status Bits.................................................. 125
Transmit/Receive Shift Register ............................... 119
Underflow Mode Control Bit...................................... 126
Word Size Selection Bits .......................................... 121
Register Map ............................................................ 153
FBORPOR ................................................................ 151
FBS........................................................................... 151
FGS .......................................................................... 151
FOSC........................................................................ 151
FSS........................................................................... 151
FWDT ....................................................................... 151
Instructions (Table) ..................................................... 16
Multiplier ..................................................................... 19
Continuous Pulse Mode.............................................. 84
Single Pulse Mode...................................................... 84
AC............................................................................. 176
DC ............................................................................ 167
Setting Up Data, Parity and Stop Bit Selections ....... 101
ADC Conversion Clock ............................................. 131
Baud Rate................................................................. 103
Bit Clock Frequency.................................................. 123
COFSG Period.......................................................... 121
Serial Clock Rate ........................................................ 96
Time Quantum for Clock Generation ........................ 113
Trap Sources .............................................................. 43
Type A, B and C Timer ............................................. 184
Type A Timer ............................................................ 184
Type B Timer ............................................................ 185
Type C Timer ............................................................ 185
AC-Link Mode................................................... 191
Multichannel, I
AC-Link Mode................................................... 191
Multichannel, I
2
2
S Modes................................... 189
S Modes................................... 190
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