DSPIC30F5011-30I/PT Microchip Technology Inc., DSPIC30F5011-30I/PT Datasheet - Page 91
DSPIC30F5011-30I/PT
Manufacturer Part Number
DSPIC30F5011-30I/PT
Description
16 BIT MCU/DSP 64LD 30MIPS 66 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F5011-30IPT.pdf
(224 pages)
Specifications of DSPIC30F5011-30I/PT
A/d Inputs
16-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
66K Bytes
Ram Size
4K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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14.3
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SSx pin
control enabled (SSEN = 1). When the SSx pin is low,
transmission and reception are enabled and the SDOx
pin is driven. When SSx pin goes high, the SDOx pin is
no longer driven. Also, the SPI module is re-
synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MSb
even if SSx had been de-asserted in the middle of a
transmit/receive.
14.4
During Sleep mode, the SPI module is shutdown. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
© 2006 Microchip Technology Inc.
Slave Select Synchronization
SPI Operation During CPU Sleep
Mode
14.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
dsPIC30F5011/5013
SPI Operation During CPU Idle
Mode
DS70116F-page 89
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