PIC24FJ64GA004-I/PT Microchip Technology Inc., PIC24FJ64GA004-I/PT Datasheet
PIC24FJ64GA004-I/PT
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PIC24FJ64GA004-I/PT Summary of contents
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... PIC24FJ64GA004 Family © 2007 Microchip Technology Inc. Data Sheet 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary DS39881B ...
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... EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , K L logo, microID, MPLAB, PIC DSCs ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ® ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Analog Features: • 10-Bit 13-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: • Peripheral Pin Select: ...
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... PIC24FJ64GA004 FAMILY Pin Diagrams (1) 28-Pin SPDIP, SSOP, SOIC AN0/V REF AN1/V REF PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 SOSCI/RP4/PMBE/CN1/RB4 SOSCO/T1CK/CN0/PMA1/RA4 (2) PGD3/EMUD3/RP5/SDA1 (1) 28-Pin QFN PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 Legend: RPn represents remappable peripheral pins. ...
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... PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “Peripheral Pin Select” and the specific peripheral sections. 2: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY SOSCI/RP4/CN1/RB4 ...
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... PIC24FJ64GA004 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V /V CAP DDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 Legend: RPn represents remappable peripheral pins. Note 1: RPn pins can be configured to function as any of the following peripherals: timers, UART, input capture, output compare, PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “ ...
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... Electrical Characteristics .......................................................................................................................................................... 223 27.0 Packaging Information.............................................................................................................................................................. 237 Appendix A: Revision History............................................................................................................................................................. 245 Index ................................................................................................................................................................................................. 247 The Microchip Web Site ..................................................................................................................................................................... 251 Customer Change Notification Service .............................................................................................................................................. 251 Customer Support .............................................................................................................................................................................. 251 Reader Response .............................................................................................................................................................................. 252 Product Identification System ............................................................................................................................................................ 253 © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 5 ...
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... PIC24FJ64GA004 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ64GA004 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. ...
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... C PIC24FJ64GA004 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels ...
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... PIC24FJ64GA004 FAMILY FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV & Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode & Control Power-up Timing OSCO/CLKO Timer Generation OSCI/CLKI Oscillator Start-up Timer FRC/LPRC ...
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... TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC AN0 2 27 AN1 3 28 AN2 4 1 AN3 5 2 AN4 6 3 AN5 7 4 AN6 — — AN7 — — AN8 — — AN9 26 23 AN10 25 22 AN11 ...
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... PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC CN0 12 9 CN1 11 8 CN2 2 27 CN3 3 28 CN4 4 1 CN5 5 2 CN6 6 3 CN7 7 4 CN8 — — CN9 — — CN10 — ...
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... TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC OSCI 9 6 OSCO 10 7 PGC1 5 2 PGD1 4 1 PGC2 22 19 PGD2 21 18 PGC3 14 12 PGD3 15 11 PMA0 10 7 PMA1 12 9 PMA2 — — PMA3 — ...
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... PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC RA0 2 27 RA1 3 28 RA2 9 6 RA3 10 7 RA4 12 9 RA7 — — RA8 — — RA9 — — RA10 — — RB0 ...
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... TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC RP0 4 1 RP1 5 2 RP2 6 3 RP3 7 4 RP4 11 8 RP5 14 11 RP6 15 12 RP7 16 13 RP8 17 14 RP9 18 15 RP10 21 18 RP11 22 19 RP12 ...
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... PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC T1CK 12 9 TCK 17 14 TDI 21 18 TDO 18 15 TMS 13 DDCAP DDCORE REF REF Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared ...
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... Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... PIC24FJ64GA004 FAMILY FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks ...
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... W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register ...
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... PIC24FJ64GA004 FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
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... PIC24FJ64GA004 FAMILY 2.3.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...
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... Program Address Space The program address memory PIC24FJ64GA004 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES PIC24FJ16GA PIC24FJ32GA GOTO Instruction GOTO Instruction Reset Address Reset Address Interrupt Vector Table ...
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... On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ64GA004 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. ...
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... Section 3.3.3 “Reading Data from Program Memory Using Program Space Visibility”). FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES MSB Address 0001h 07FFh ...
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... PIC24FJ64GA004 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 27 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 28 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 29 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 30 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 31 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 33 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 34 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 35 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 36 Preliminary © 2007 Microchip Technology Inc. ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 3.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... PIC24FJ64GA004 FAMILY TABLE 3-25: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) Configuration Program Space Visibility User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG< ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the “phantom byte”, will always be ‘0’. ...
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... PIC24FJ64GA004 FAMILY 3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i ...
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... Run-Time Self-Programming (RTSP) • JTAG • Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FJ64GA004 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGCx ...
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... PIC24FJ64GA004 FAMILY 4.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY (1) U-0 U-0 — — (1) U-0 ...
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... PIC24FJ64GA004 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of program Flash memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
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... W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR BTSC NVMCON, #15 BRA $-2 © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...
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... PIC24FJ64GA004 FAMILY 4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH ...
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... Reset Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized W Register © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A Power-on Reset will clear all bits except for the BOR and POR bits (RCON< ...
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... PIC24FJ64GA004 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Setting Event 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... PIC24FJ64GA004 FAMILY TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source POR EC, FRC, FRCDIV, LPRC T ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL MCLR Any Clock WDT Any Clock ...
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... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 52 Preliminary © 2007 Microchip Technology Inc. ...
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... These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
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... PIC24FJ64GA004 FAMILY FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 52 ...
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... SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter LVD Low-Voltage Detect © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Vector AIVT IVT Address Number Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah 00019Ah ...
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... PIC24FJ64GA004 FAMILY 6.3 Interrupt Control and Status Registers The PIC24FJ64GA004 family of devices implement a total of 28 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0 through IFS4 • IEC0 through IEC4 • IPC0 through IPC12, IPC15, IPC16 and IPC18 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
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... See Register 2-2 for the description of remaining bit (s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 — — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 — — PMPIF bit 15 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8 ...
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... Interrupt request enabled 0 = Interrupt request not enabled Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPx pin. See Section 9.4 ”Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 — RTCIE — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit ...
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... Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP2 T1IP1 bit 15 U-0 R/W-1 R/W-0 — IC1IP2 IC1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP2 U1RXIP1 bit 15 U-0 R/W-1 R/W-0 — SPF1IP2 SPF1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP2 CNIP1 bit 15 U-0 R/W-1 R/W-0 — MI2C1P2 MI2C1P1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 — T4IP2 T4IP1 bit 15 U-0 R/W-1 R/W-0 — OC3IP2 OC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... Unimplemented: Read as ‘0’ bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SPI2IP2 SPI2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
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... IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — OC5IP2 OC5IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
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... SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 U-0 U-0 SI2C2P0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 ...
Page 85
... U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — ...
Page 86
... PIC24FJ64GA004 FAMILY REGISTER 6-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ bit 12-0 ...
Page 87
... RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 88
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 86 Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... PIC24F devices not intended comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual” chapter. The oscillator system for PIC24FJ64GA004 family devices has the following features: FIGURE 7-1: PIC24FJ64GA004 FAMILY CLOCK DIAGRAM Primary Oscillator OSCO ...
Page 90
... PIC24FJ64GA004 FAMILY 7.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 4x PLL ...
Page 91
... It controls clock source switching and allows the monitoring of clock sources. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY The Clock Divider register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...
Page 92
... PIC24FJ64GA004 FAMILY REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC2 COSC1 bit 15 R/SO-0 R/W-0 R-0 (2) CLKLOCK IOLOCK LOCK bit 7 Legend Clear-Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 93
... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 91 ...
Page 94
... PIC24FJ64GA004 FAMILY REGISTER 7-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-0 ROI DOZE2 DOZE1 bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 ...
Page 95
... POSCMDx Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...
Page 96
... PIC24FJ64GA004 FAMILY 7.4.2 OSCILLATOR SWITCHING SEQUENCE At a minimum, performing a clock switch requires this basic sequence desired, read the COSCx (OSCCON<14:12>), to determine the current oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. Write the appropriate value to the NOSCx bits (OSCCON< ...
Page 97
... For more information, refer to the associated “PIC24F Family Reference Manual” chapter. The PIC24FJ64GA004 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...
Page 98
... PIC24FJ64GA004 FAMILY 8.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “ ...
Page 99
... Data Latch Read LAT Read PORT © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 100
... DS39881B-page 98 9.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ64GA004 family of devices to gen- erate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. Depending ...
Page 101
... C™, change notification inputs, RTCC alarm outputs or peripherals with analog inputs. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A key difference between pin select and non pin select peripherals is that pin select peripherals are not asso- ciated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used ...
Page 102
... PIC24FJ64GA004 FAMILY TABLE 9-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Timer4 External Clock Timer5 External Clock Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Output Compare Fault A ...
Page 103
... Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 9.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed; attempted writes will appear to execute normally, but the contents of the registers will remain unchanged ...
Page 104
... PIC24FJ64GA004 FAMILY 9.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the peripheral pin selects are not available on default pins in the device’ ...
Page 105
... Peripheral Pin Select Registers The PIC24FJ64GA004 family of devices implements a total of 27 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (14) • Output Remappable Peripheral Registers (13) REGISTER 9-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — ...
Page 106
... PIC24FJ64GA004 FAMILY REGISTER 9-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 107
... IC4R4:IC4R0: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R4:IC3R0: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 IC2R4 IC2R3 IC2R2 ...
Page 108
... PIC24FJ64GA004 FAMILY REGISTER 9-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 109
... U2CTSR4:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U2RXR4:U2RXR0: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 U1CTSR3 ...
Page 110
... PIC24FJ64GA004 FAMILY REGISTER 9-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 111
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R4:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 R/W-1 ...
Page 112
... PIC24FJ64GA004 FAMILY REGISTER 9-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 113
... Unimplemented: Read as ‘0’ bit 4-0 RP6R4:RP6R0: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP5R4 RP5R3 RP5R2 R/W-0 ...
Page 114
... PIC24FJ64GA004 FAMILY REGISTER 9-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 115
... Unimplemented: Read as ‘0’ bit 4-0 RP14R4:RP14R0: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 RP13R3 RP13R2 R/W-0 ...
Page 116
... PIC24FJ64GA004 FAMILY REGISTER 9-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 117
... Unimplemented: Read as ‘0’ bit 4-0 RP22R4:RP22R0: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 RP21R3 RP21R2 R/W-0 ...
Page 118
... PIC24FJ64GA004 FAMILY REGISTER 9-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 119
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 120
... PIC24FJ64GA004 FAMILY REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 121
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). 2. ...
Page 122
... PIC24FJ64GA004 FAMILY FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) ADC Event Trigger Equal MSB Reset Read TMR2 (TMR4) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...
Page 123
... Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. 2: The ADC Event Trigger is available only on Timer4/5. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 1x Gate Sync 01 00 ...
Page 124
... PIC24FJ64GA004 FAMILY REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When TxCON<3> ...
Page 125
... When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 (1) — — ...
Page 126
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 124 Preliminary © 2007 Microchip Technology Inc. ...
Page 127
... An ‘x’ signal, register or bit name denotes the number of the capture channel. 2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY comprehensive FIFO Edge Detection Logic R/W ...
Page 128
... PIC24FJ64GA004 FAMILY 12.1 Input Capture Registers REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 129
... OCxIE bit. For further information on peripheral interrupts, refer to Section 6.0 “Interrupt Controller”. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘100’. ...
Page 130
... PIC24FJ64GA004 FAMILY 13.3 Pulse-Width Modulation Mode Note: This peripheral contains input and output functions that may need to be configured by the peripheral pin Section 9.4 “Peripheral Pin Select” for more information. The following steps should be taken when configuring the output compare module for PWM operation: 1 ...
Page 131
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Note 1: Based /2; Doze mode and PLL are disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • (Timer 2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 FFFFh ...
Page 132
... PIC24FJ64GA004 FAMILY FIGURE 13-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM (1) OCxRS (1) OCxR Comparator OCTSEL TMR register inputs from time bases (see Note 3). Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. ...
Page 133
... RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
Page 134
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 132 Preliminary © 2007 Microchip Technology Inc. ...
Page 135
... Block diagrams of the module in Standard and Enhanced modes are shown in Figure 14-1 and Figure 14-2. Depending on the pin count, devices of the PIC24FJ64GA004 family offer one or two SPI modules on a single device. Note: In this section, the SPI modules are referred to together as SPIx or separately as SPI1 and SPI2 ...
Page 136
... PIC24FJ64GA004 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register. 2. Write the desired settings to the SPIxCON1 and ...
Page 137
... Control Control Clock SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer 8-Level FIFO Transmit Buffer Write SPIxBUF 16 Internal Data Bus Preliminary ...
Page 138
... PIC24FJ64GA004 FAMILY REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 (1) SPIEN — SPISIDL bit 15 R-0 R/C-0 R/W-0 SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 139
... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 137 ...
Page 140
... PIC24FJ64GA004 FAMILY REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (4) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 141
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...
Page 142
... PIC24FJ64GA004 FAMILY FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF) MSTEN (SPIxCON1<5> Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF ...
Page 143
... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx ...
Page 144
... PIC24FJ64GA004 FAMILY EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based TABLE 14-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: Based /2; Doze mode and PLL are disabled SCKx frequencies shown in kHz. DS39881B-page 142 ...
Page 145
... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 15-1. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 15.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 146
... PIC24FJ64GA004 FAMILY 2 FIGURE 15-1: I C™ BLOCK DIAGRAM Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39881B-page 144 I2CxRCV I2CxRSR LSB Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 147
... I C peripheral operating in Slave mode. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY module to respond whether the corresponding address bit value is a ‘0’ ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both addresses, ‘0000000’ and ‘00100000’. ...
Page 148
... PIC24FJ64GA004 FAMILY 2 TABLE 15-2: I C™ RESERVED ADDRESSES Slave R/W Address Bit General Call Address 0000 000 0 Start Byte 0000 000 1 Cbus Address 0000 001 x Reserved 0000 010 x Reserved 0000 011 x HS Mode Master Code 0000 1xx x Reserved 1111 1xx x 10-bit slave upper byte ...
Page 149
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enables software or receive clock stretching 0 = Disables software or receive clock stretching © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 150
... PIC24FJ64GA004 FAMILY REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (When operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as I receive ...
Page 151
... Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/C-0, HS — ...
Page 152
... PIC24FJ64GA004 FAMILY REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected ...
Page 153
... AMSK9:AMSK0: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...
Page 154
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 152 Preliminary © 2007 Microchip Technology Inc. ...
Page 155
... This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • One or Two Stop bits • Hardware Flow Control Option with UxCTS and UxRTS Pins • ...
Page 156
... PIC24FJ64GA004 FAMILY 16.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 16-1: ...
Page 157
... FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Section 16.2 “Transmitting in 8-Bit Data Mode”). ...
Page 158
... PIC24FJ64GA004 FAMILY REGISTER 16-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Cleared bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 159
... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). 3: Bit availability depends on pin availability. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 157 ...
Page 160
... PIC24FJ64GA004 FAMILY REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 161
... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1 UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 159 ...
Page 162
... PIC24FJ64GA004 FAMILY REGISTER 16-3: UxTXREG: UARTx TRANSMIT REGISTER U-x U-x U-x — — — bit 15 W-x W-x W-x UTX7 UTX6 UTX5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 -9 Unimplemented: Read as ‘0’ bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode) ...
Page 163
... Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. Note: A number of the pins for the PMP are not present on PIC24FJ64GA004 devices. Refer to the specific device’s pinout to determine which pins are available. FIGURE 17-1: PMP MODULE OVERVIEW ...
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... PIC24FJ64GA004 FAMILY REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 PMPEN — PSIDL bit 15 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PMPEN: Parallel Master Port Enable bit ...
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... For Master mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: Devices with 28 pins do not have PMA<10:2>. 2: These bits have no effect when their corresponding pins are used as address lines. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 163 ...
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... PIC24FJ64GA004 FAMILY REGISTER 17-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 15 R/W-0 R/W-0 R/W-0 (1) (1) WAITB1 WAITB0 WAITM3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 BUSY: Busy bit (Master mode only) ...
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... PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Note 1: Devices with 28 pins do not have PMA<10:2>. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-0 — — R/W-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 17-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 IBF IBOV — bit 15 R-1 R/W-0, HS U-0 OBE OBUF — bit 7 Legend Hardware Set bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IBF: Input Buffer Full Status bit ...
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... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
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... PIC24FJ64GA004 FAMILY FIGURE 17-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PMD<7:0> PMCS1 PMRD PMWR FIGURE 17-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PMA<1:0> PMD<7:0> PMCS1 PMRD PMWR Address Bus Data Bus Control Lines TABLE 17-1: SLAVE MODE ADDRESS RESOLUTION PMA<1:0> Output Register (Buffer) ...
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... PMALL PMALH PMCS1 PMRD PMWR FIGURE 17-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<10:8> PMCS1 PMRD PMWR © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PMA<10:8> PMD<7:0> PMA<7:0> PMCS1 PMALL PMRD PMWR PMD<7:0> PMA<7:0> PMA<15:8> PMCS1 PMALL PMALH PMRD PMWR A< ...
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... PIC24FJ64GA004 FAMILY FIGURE 17-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F PMD<7:0> PMALL PMCS1 PMRD PMWR FIGURE 17-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA) PIC24F PMA<n:0> PMD<7:0> PMCS1 PMRD PMWR FIGURE 17-11: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA) PIC24F PMA< ...
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... Input from SOSC Oscillator RTCC Prescalers RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY CPU Clock Domain RCFGCAL ALCFGRPT 0.5s RTCVAL ALRMVAL RTCC Interrupt Logic Preliminary YEAR MTHDAY WKDYHR ...
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... PIC24FJ64GA004 FAMILY 18.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 18.1.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corre- sponding register pointers ...
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... The RCFGCAL register is only affected by a POR write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R-0 R-0 R/W-0 (3) RTCSYNC HALFSEC ...
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... PIC24FJ64GA004 FAMILY REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER bit 7-0 CAL7:CAL0: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment ...
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... Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 ...
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... PIC24FJ64GA004 FAMILY 18.1.4 RTCVAL REGISTER MAPPINGS REGISTER 18-4: YEAR: YEAR VALUE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
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... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-x — — ...
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... PIC24FJ64GA004 FAMILY 18.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 18-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-x — — DAYTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘ ...
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... Once the error is known, it must be converted to the number of error clock pulses per minute. EQUATION 18-1: (Ideal Frequency† – Measured Frequency Clocks per Minute † Ideal frequency = 32,768 Hz © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-x R/W-x R/W-x MINTEN0 MINONE3 MINONE2 ...
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... PIC24FJ64GA004 FAMILY 18.3 Alarm • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT<7>, Register 18-3) • One-time alarm and repeat alarm options available 18.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVALH:ALRMVALL should only take place when ALRMEN = 0 ...
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... Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 19.1 Registers There are four registers used to control programmable CRC operation: • CRCCON • ...
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... PIC24FJ64GA004 FAMILY REGISTER 19-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 X15 X14 X13 bit 15 R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-1 X15:X1: XOR of Polynomial Term X bit 0 Unimplemented: Read as ‘0’ ...
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... IN BIT 0 D OUT 1 p_clk © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY TABLE 19-1: Bit Name PLEN3:PLEN0 X<15:1> Note that for the value of X<15:1>, the 12th bit and the 5th bit are set to ‘1’, as required by the equation. The 0th bit required by the equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed ...
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... PIC24FJ64GA004 FAMILY FIGURE 19-2: CRC GENERATOR RECONFIGURED FOR x XOR SDOx BIT 0 BIT 4 p_clk p_clk 19.3 User Interface 19.3.1 DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (PLEN<3:0>) > 7, and 16 deep, otherwise. The data for which the CRC calculated must first be written into the FIFO ...
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... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A block diagram of the A/D Converter is shown in Figure 20-1. To perform an A/D conversion: 1. ...
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... PIC24FJ64GA004 FAMILY FIGURE 20-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM REF REF AN0 V INH AN1 AN2 AN3 AN4 V INL AN5 AN6 AN7 AN8 V AN9 V AN10 AN11 AN12 Note 1: Devices with 28 pins can only use AN0-AN5 and AN9-AN12. DS39881B-page 186 V INH S/H ...
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... SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 20-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 bit 15 R-0 U-0 R/W-0 BUFS — SMPI3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG2:VCFG0: Voltage Reference Configuration bits VCFG2:VCFG0 ...
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... AD bit 7-0 ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 128 • ······ 00000001 = T CY 00000000 = © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘ ...
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... PIC24FJ64GA004 FAMILY REGISTER 20-4: AD1CHS0: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — bit 15 R/W-0 U-0 U-0 CH0NA — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit ...
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... CSSL12:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Note 1: Devices with 28 pins can use only CSSL0-CSSL5 and CSSL9-CSSL12. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 ...
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... PIC24FJ64GA004 FAMILY EQUATION 20-1: A/D CONVERSION CLOCK PERIOD Note 1: Based on T FIGURE 20-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL ANx PIN 6-11 pF (Typical) Legend: C Note: C value depends on device package and is not tested. Effect of C PIN DS39881B-page 192 ( (ADCS + – 1 ADCS = ...
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... Voltage Level © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 193 ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 194 Preliminary © 2007 Microchip Technology Inc. ...
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... IN C2IN- C2POS C2IN REF Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY C1EN C1INV - C1 + C2EN C2INV - C2 + Preliminary CMCON<6> ...
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... PIC24FJ64GA004 FAMILY REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/C-0 CMIDL — C2EVT bit 15 R-0 R-0 R/W-0 C2OUT C1OUT C2INV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CMIDL: Stop in Idle Mode 1 = When device enters Idle mode, module does not generate interrupts. Module is still enabled. ...
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... If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See Section 9.4 “Peripheral Pin Select” for more information C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY + ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 198 Preliminary © 2007 Microchip Technology Inc. ...