PIC24FJ64GA004-I/PT Microchip Technology Inc., PIC24FJ64GA004-I/PT Datasheet - Page 103

• Manufacturer Part Number: PIC24FJ64GA004-I/PT
• Description: MCU, 16-Bit, 44-Pin, 64KB Flash, 8KB RAM, 35 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA004-I/PT

• A/d Inputs: 13 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 35
• Number Of Pins: 44
• Package Type: 44-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 9-2:
9.4.3.3
The control schema of the peripheral pin select is
extremely flexible. Other than systematic blocks that
prevent signal contention caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lock outs. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
9.4.4
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
© 2007 Microchip Technology Inc.
NULL
C1OUT
C2OUT
U1TX
U1RTS
U2TX
U2RTS
SDO1
SCK1OUT
SS1OUT
SDO2
SCK2OUT
SS2OUT
OC1
OC2
OC3
OC4
OC5
Note 1:
Function
(2)
2:
3:
(3)
(3)
Value assigned to the RPn<4:0> pins corre-
sponds to the peripheral output function
number.
The NULL function is assigned to all RPn
outputs at device Reset and disables the
RPn output function.
IrDA
CONTROLLING CONFIGURATION
CHANGES
Output Function
Mapping Limitations
Number
®
BCLK functionality uses this output.
SELECTABLE OUTPUT
SOURCES (MAPS FUNCTION
TO OUTPUT)
10
11
12
18
19
20
21
22
0
1
2
3
4
5
6
7
8
9
(1)
NULL
Comparator 1 Output
Comparator 2 Output
UART1 Transmit
UART1 Request To Send
UART2 Transmit
UART2 Request To Send
SPI1 Data Output
SPI1 Clock Output
SPI1 Slave Select Output
SPI2 Data Output
SPI2 Clock Output
SPI2 Slave Select Output
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Output Compare 5
Output Name
PIC24FJ64GA004 FAMILY
Preliminary
9.4.4.1
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed; attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
9.4.4.2
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
9.4.4.3
As an additional level of safety, the device can be con-
figured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(CW2<4>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the peripheral pin select control regis-
ters cannot be written to. The only way to clear the bit
and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the peripheral
pin select registers.
Write 46h to OSCCON<7:0>.
Write 57h to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
Control Register Lock
Continuous State Monitoring
Configuration Bit Pin Select Lock
DS39881B-page 101