PIC24FJ64GA004-I/PT Microchip Technology Inc., PIC24FJ64GA004-I/PT Datasheet - Page 105
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PIC24FJ64GA004-I/PT
Manufacturer Part Number
PIC24FJ64GA004-I/PT
Description
MCU, 16-Bit, 44-Pin, 64KB Flash, 8KB RAM, 35 I/O, Nanowatt
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24FJ64GA004-IPT.pdf
(256 pages)
Specifications of PIC24FJ64GA004-I/PT
A/d Inputs
13 Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
35
Interface
I2C/SPI/UART
Memory Capacity
64 Kbytes
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
35
Number Of Pins
44
Package Type
44-pin TQFP
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Speed
32 MHz
Timers
5-16-bit
Voltage, Range
2-3.6 V
Voltage, Rating
2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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9.5
The PIC24FJ64GA004 family of devices implements a
total of 27 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (14)
• Output Remappable Peripheral Registers (13)
REGISTER 9-1:
REGISTER 9-2:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-8
bit 7-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-5
bit 4-0
U-0
U-0
U-0
U-0
—
—
—
—
Peripheral Pin Select Registers
Unimplemented: Read as ‘0’
INTR1R4:INTR1R0: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
INTR2R4:INTR2R0: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
U-0
U-0
U-0
U-0
—
—
—
—
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
U-0
U-0
U-0
U-0
—
—
—
—
INTR1R4
INTR2R4
R/W-1
R/W-1
PIC24FJ64GA004 FAMILY
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
INTR1R3
INTR2R3
R/W-1
R/W-1
U-0
U-0
—
—
Note:
Input and output register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 9.4.4.1 “Control Register
Lock” for a specific command sequence.
INTR1R2
INTR2R2
R/W-1
R/W-1
U-0
U-0
—
—
x = Bit is unknown
x = Bit is unknown
INTR1R1
INTR2R1
R/W-1
R/W-1
U-0
U-0
—
—
DS39881B-page 103
INTR1R0
INTR2R0
R/W-1
R/W-1
U-0
U-0
—
—
bit 8
bit 0
bit 8
bit 0
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