PIC24FJ64GA004-I/PT Microchip Technology Inc., PIC24FJ64GA004-I/PT Datasheet - Page 163
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PIC24FJ64GA004-I/PT
Manufacturer Part Number
PIC24FJ64GA004-I/PT
Description
MCU, 16-Bit, 44-Pin, 64KB Flash, 8KB RAM, 35 I/O, Nanowatt
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24FJ64GA004-IPT.pdf
(256 pages)
Specifications of PIC24FJ64GA004-I/PT
A/d Inputs
13 Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
35
Interface
I2C/SPI/UART
Memory Capacity
64 Kbytes
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
35
Number Of Pins
44
Package Type
44-pin TQFP
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Speed
32 MHz
Timers
5-16-bit
Voltage, Range
2-3.6 V
Voltage, Rating
2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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17.0
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communicate
with a wide variety of parallel devices, such as commu-
nication peripherals, LCDs, external memory devices
and microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP is highly
configurable.
FIGURE 17-1:
© 2007 Microchip Technology Inc.
Note:
Note:
Note 1:
Parallel Master Port
PARALLEL MASTER PORT
(PMP)
PIC24F
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
A number of the pins for the PMP are not
present on PIC24FJ64GA004 devices.
Refer to the specific device’s pinout to
determine which pins are available.
Devices with 28 pins do not have PMA<10:2>.
PMP MODULE OVERVIEW
(1)
PMA<0>
PMALL
PMA<1>
PMALH
PMA<10:2>
PMCS1
PMBE
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
PIC24FJ64GA004 FAMILY
Preliminary
Microcontroller
Key features of the PMP module include:
• Up to 16 Programmable Address Lines
• One Chip Select Line
• Programmable Strobe Options
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
• Programmable Wait States
• Selectable Input Voltage Levels
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
Up to 11-Bit Address
8-Bit Data
LCD
Address Bus
Data Bus
Control Lines
Buffer
FIFO
DS39881B-page 161
EEPROM
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