ICS1893Y-10 IDT, Integrated Device Technology Inc, ICS1893Y-10 Datasheet - Page 99
![PHYCEIVER LOW PWR 3.3V 64-TQFP](/photos/31/27/312736/64pin_tqfp_sml.jpg)
ICS1893Y-10
Manufacturer Part Number
ICS1893Y-10
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893Y-10
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Not Compliant
Other names
1893Y-10
800-1934-5
ICS1893Y-10
800-1934-5
ICS1893Y-10
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8.13.8 Link Loss Inhibit (bit 18.1)
8.13.9 Squelch Inhibit (bit 18.0)
ICS1893 Rev C 6/6/00
The Link Loss Inhibit bit allows an STA to prevent the ICS1893 from dropping the link in 10Base-T mode.
When an STA sets this bit to logic:
•
•
The Squelch Inhibit bit allows an STA to control the ICS1893 Squelch Detection in 10Base-T mode. When
an STA sets this bit to logic:
•
•
Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
One, the ICS1893 10Base-T Link Integrity Test state machine is forced into the ‘ Link Passed’ state
regardless of the Twisted-Pair Receiver input conditions.
Zero, before the ICS1893 can establish a valid link, the ICS1893 must receive valid 10Base-T data.
One, before the ICS1893 can establish a valid link, the ICS1893 must receive both valid 10Base-T data
followed by an IDL.
ICS1893 - Release
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
99
Chapter 8 Management Register Set
June, 2000