PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 184

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
15.3.3
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
TABLE 15-1:
TABLE 15-2:
DS41250E-page 182
0Bh,8Bh,
10Bh, 18Bh
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
Legend:
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
Address
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the RC5/T1CKI/CCP1/SEG10 pin an
output by clearing the TRISC<5> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
PWM Frequency
TRISC
TMR1L
INTCON
PIR1
PIR2
PIE1
PIE2
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
SETUP FOR PWM OPERATION
x = unknown, u = unchanged,
Name
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
T1GINV
TRISC7
OSFIF
OSFIE
Bit 7
EEIF
EEIE
GIE
—
—
TRISC6
T1GE
PEIE
ADIF
ADIE
Bit 6
C2IF
C2IE
—
—
-
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
= unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
TRISC5
CCP1X
CCP2X
1.22 kHz
RCIE
Bit 5
RCIF
T0IE
C1IF
C1IE
0xFFh
16
10
TRISC4
CCP1Y
CCP2Y
LCDIF
LCDIE
Bit 4
INTE
TXIF
TXIE
Preliminary
4.88 kHz
0xFFh
10
4
CCP1M3
CCP2M3
TRISC3
SSPIF
SSPIE
Bit 3
RBIE
—
—
19.53 kHz
0xFFh
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CCP1IE
TRISC2
CCP1IF
10
LVDIF
LVDIE
Bit 2
1
T0IF
TMR2IE
TMR2IF
TRISC1
Bit 1
INTF
78.12kHz
—
—
0x3Fh
1
8
TMR1IF
CCP2IF
TMR1IE
CCP2IE
TRISC0
© 2005 Microchip Technology Inc.
RBIF
Bit 0
156.3 kHz
0x1Fh
0000 000x 0000 000x
0000 0000 0000 0000
0000 -0-0 0000 -0-0
0000 0000 0000 0000
0000 -0-0 0000 -0-0
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on:
1
7
POR,
BOR
208.3 kHz
0x17h
Value on
all other
Resets
5.5
1