PIC16F1939-I/PT Microchip Technology Inc., PIC16F1939-I/PT Datasheet - Page 138

• Manufacturer Part Number: PIC16F1939-I/PT
• Description: 44 TQFP 10x10x1mm TRAY, 28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1939-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin TQFP
• Programmable Memory: 28K Bytes
• Ram Size: 1K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F193X/LF193X
REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER
TABLE 12-3:
DS41364D-page 138
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
Note 1:
ADCON0
ANSELB
APFCON
CCPxCON
CPSCON0
CPSCON1
INTCON
IOCBP
IOCBN
IOCBF
LATB
LCDCON
LCDSE0
LCDSE1
OPTION_REG
PORTB
T1GCON
TRISB
WPUB
Legend:
Note 1:
R/W-1/1
WPUB7
Name
2:
Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936 devices.
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
TMR1GE
IOCBP7
IOCBN7
IOCBF7
WPUEN
WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
CPSON
TRISB7
WPUB7
LCDEN
LATB7
SE15
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB7
SE7
GIE
R/W-1/1
WPUB6
—
—
—
—
PxM<1:0>
CCP3SEL
CPSRM
T1GPOL
INTEDG
IOCBP6
IOCBN6
IOCBF6
TRISB6
WPUB6
SLPEN
LATB6
SE14
PEIE
Bit 6
SE6
RB6
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-1/1
WPUB5
(1)
TMR0CS
T1GSEL
TMR0IE
IOCBP5
IOCBN5
IOCBF5
TRISB5
WPUB5
T1GTM
ANSB5
WERR
LATB5
SE13
Bit 5
SE5
RB5
—
—
DCxB<1:0>
R/W-1/1
WPUB4
TMR0SE
T1GSPM
P2BSEL
IOCBN4
IOCBP4
IOCBF4
TRISB4
WPUB4
ANSB4
LATB4
Preliminary
CHS<4:0>
SE12
INTE
Bit 4
SE4
RB4
—
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
T1GGO/DONE
SRNQSEL
R/W-1/1
WPUB3
IOCBN3
IOCBP3
IOCBF3
WPUB3
TRISB3
ANSB3
LATB3
IOCIE
SE11
Bit 3
SE3
PSA
RB3
CPSRNG<1:0>
CS<1:0>
C2OUTSEL
IOCBN2
T1GVAL
TMR0IF
IOCBP2
IOCBF2
TRISB2
WPUB2
ANSB2
R/W-1/1
LATB2
WPUB2
CCPxM<3:0>
SE10
Bit 2
RB2
CPSCH<3:>
SE2
GO/DONE
CPSOUT
PS<2:0>
IOCBN1
 2009 Microchip Technology Inc.
IOCBP1
IOCBF1
WPUB1
TRISB1
ANSB1
SSSEL
LATB1
Bit 1
INTF
SE1
SE9
RB1
T1GSS<1:0>
LMUX<1:0>
R/W-1/1
WPUB1
CCP2SEL
IOCBN0
IOCBP0
IOCBF0
WPUB0
TRISB0
ANSB0
T0XCS
LATB0
ADON
IOCIF
Bit 0
SE0
SE8
RB0
R/W-1/1
WPUB0
Register
on Page
161
137
130
231
323
324
150
150
150
137
329
333
333
191
136
202
137
138
99
bit 0