PIC16F1939-I/PT Microchip Technology Inc., PIC16F1939-I/PT Datasheet - Page 267

• Manufacturer Part Number: PIC16F1939-I/PT
• Description: 44 TQFP 10x10x1mm TRAY, 28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1939-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin TQFP
• Programmable Memory: 28K Bytes
• Ram Size: 1K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

23.5.8
The addressing procedure for the I
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
The general call address is a reserved address in the
I
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software
Figure 23-23
sequence.
FIGURE 23-24:
23.5.9
An SSP Mask (SSPMSK) register (Register 23-5) is
available in I
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
 2009 Microchip Technology Inc.
2
C protocol, defined as address 0x00. When the
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
GCEN (SSPCON2<7>)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
can
GENERAL CALL ADDRESS
SUPPORT
SSP MASK REGISTER
2
C Slave mode as a mask for the value
shows
read
S
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
a
1
SSPBUF
general
2
General Call Address
2
3
C bus is such that
and
call
4
reception
5
respond.
6
Preliminary
7
R/W =
8
0
ACK
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
Address is compared to General Call Address
after ACK, set interrupt
9
PIC16F193X/LF193X
D7
1
D6
2
Cleared by software
SSPBUF is read
Receiving Data
D5
3
D4
4
D3
5
D2
6
D1
7
DS41364D-page 267
D0
8
ACK
9
’1’