PIC16F1939-I/PT Microchip Technology Inc., PIC16F1939-I/PT Datasheet - Page 46

• Manufacturer Part Number: PIC16F1939-I/PT
• Description: 44 TQFP 10x10x1mm TRAY, 28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1939-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin TQFP
• Programmable Memory: 28K Bytes
• Ram Size: 1K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F193X/LF193X
TABLE 3-14:
DS41364D-page 46
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
Legend:
Note
Address
Bank 5
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1, 2)
(2)
1:
2:
3:
4:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPTMRS1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are trans-
ferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices.
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
CCP1ASE
Unimplemented
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
CCP2ASE
C4TSEL1
P1RSEN
P2RSEN
Bit 7
GIE
—
—
—
—
—
—
P1M<1:0>
P2M<1:0>
Write Buffer for the upper 7 bits of the Program Counter
C4TSEL0
Bit 6
PEIE
—
—
—
—
—
CCP1AS<2:0>
CCP2AS<2:0>
C3TSEL1
TMR0IE
Bit 5
—
—
—
—
—
DC1B<1:0>
DC2B<1:0>
Preliminary
STR1SYNC
STR2SYNC
C3TSEL0
INTE
Bit 4
TO
—
P1DC<6:0>
P2DC<6:0>
C2TSEL1
STR1D
STR2D
IOCIE
Bit 3
PD
PSS1AC<1:0>
PSS2AC<1:0>
—
BSR<4:0>
C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
TMR0IF
STR1C
STR2C
Bit 2
CCP1M<3:0>
CCP2M<3:0>
—
Z
STR1B
STR2B
INTF
Bit 1
DC
PSS1BD<1:0>
PSS2BD<1:0>
C5TSEL<1:0>
 2009 Microchip Technology Inc.
STR1A
STR2A
IOCIF
Bit 0
C
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
---0 0001 ---0 0001
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
---0 0001 ---0 0001
---- --00 ---- --00
POR, BOR
Value on:
—
—
—
—
—
—
Value on all
Resets
other
—
—
—
—
—
—