DS80C310-MCG+ Dallas Semiconductor, DS80C310-MCG+ Datasheet - Page 12

• Manufacturer Part Number: DS80C310-MCG+
• Description: 8BIT CISC ROMLESS 25MHZ 5V 40PDIP
• Manufacturer: Dallas Semiconductor

Specifications of DS80C310-MCG+

• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: UART
• Memory Type: ROMless
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 0 Bytes
• Ram Size: 256 Bytes
• Speed: 25 MHz
• Timers: 3-16-bit
• Voltage, Range: 4-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

Figure 2. Typical I
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
cycles following 1 to 0 transitions, the typical current sink capability of Port 0 and Port 2 is approximately 150µA, and the
minimum current sink capability of ALE and PSEN is approximately 400µA. On subsequent cycles following 0 to 1
transitions, the typical current drive capability of Port 0 and Port 2 is approximately 110µA.
mode.
This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin must also overcome the transition
current.
2V.
address bus on the DS80C310. Peak current occurs near the input transition point of the latch, approximately 2V.
When addressing external memory. This specification applies to the first clock cycle following the transition. On subsequent
RST = V
During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition
Current required from external circuit to hold a logic-low level on an I/O pin while the corresponding port latch bit is set to 1.
Ports 1 and 3 source transition current when being pulled down externally. The current reaches its maximum at approximately
0.45 < V
IN
CC
. This condition mimics operation of pins in I/O mode.
<V
CC
CC
. Not a high-impedance input. This port is a weak address holding latch because Port 0 is dedicated as an
vs. Frequency
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DS80C310