DS80C310-MCG+ Dallas Semiconductor, DS80C310-MCG+ Datasheet - Page 9

• Manufacturer Part Number: DS80C310-MCG+
• Description: 8BIT CISC ROMLESS 25MHZ 5V 40PDIP
• Manufacturer: Dallas Semiconductor

Specifications of DS80C310-MCG+

• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: UART
• Memory Type: ROMless
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 0 Bytes
• Ram Size: 256 Bytes
• Speed: 25 MHz
• Timers: 3-16-bit
• Voltage, Range: 4-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

Table 2. Data Memory Cycle Stretch Values
DUAL DATA POINTER (DPTR)
Data memory block moves can be accelerated using the DS80C310 dual data pointer (DPTR). The
standard 8032 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS80C310, the standard data pointer is called DPTR and is located at SFR addresses 82h and 83h. These
are the standard locations. No modification of standard code is needed to use DPTR. The new DPTR is
located at SFR 84h and 85h and is called DPTR1. The DPTR select bit (DPS) chooses the active pointer
and is located at the LSB of the SFR location 86h. No other bits in register 86h have any effect and are set
to 0. The user switches between data pointers by toggling the LSB of register 86h. The increment (INC)
instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected
DPTR for any activity. Therefore, only one instruction is required to switch from a source to a destination
address. Using the DPTR saves code from needing to save source and destination addresses when doing a
block move. Once loaded, the software simply switches between DPTR0 and 1. The relevant register
locations are as follows.
STOP MODE ENHANCEMENTS
Setting bit 1 of the Power Control Register (PCON; 87h) invokes the stop mode. Stop mode is the lowest
power state because it turns off all internal clocking. The I
1 µ A (but is specified in the Absolute Maximum Ratings section). The CPU exits stop mode from an
external interrupt or a reset condition. Internally generated interrupts are not useful since they require
clocking activity.
The DS80C310 allows a resume from stop using INT2–INT5, which are edge-triggered interrupts. An
internal crystal counter manages the startup timing. A delay of 65,536 clocks occurs to allow the crystal
time to stabilize. Software must also insert a delay of 100 machine cycles following the exit from stop
mode. This ensures stabilization of internal timing prior to time-critical software tasks such as serial port
operations or bus access to memory-mapped I/O devices.
CKCON.2–CKCON.0
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
DPL
DPH
DPL1
DPH1
DPS
MEMORY
3 (default)
CYCLES
2
4
5
6
7
8
9
82h
83h
84h
85h
86h
9 of 24
STROE WIDTH
RD OR WR
12
16
20
24
28
2
4
8
Low byte original DPTR
High byte original DPTR
Low byte new DPTR
High byte new DPTR
DPTR Select (lsb)
CC
of a standard stop mode is approximately
At 25MHz
STROBE WIDTH TIME (ns)
1120
160
320
480
640
800
960
80
At 33MHz
121
242
364
485
606
727
848
60
DS80C310