DS80C310-MCG+ Dallas Semiconductor, DS80C310-MCG+ Datasheet - Page 4

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DS80C310-MCG+

Manufacturer Part Number
DS80C310-MCG+
Description
8BIT CISC ROMLESS 25MHZ 5V 40PDIP
Manufacturer
Dallas Semiconductor
Datasheet

Specifications of DS80C310-MCG+

Eeprom Memory
0 Bytes
Input Output
32
Interface
UART
Memory Type
ROMless
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
0 Bytes
Ram Size
256 Bytes
Speed
25 MHz
Timers
3-16-bit
Voltage, Range
4-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
10–17
18, 19
PDIP
20
21
22
23
24
25
26
27
28
PLCC
13–19
20, 21
1, 22,
11,
PIN
23
24
25
26
27
28
29
30
31
5, 7–13
16, 17,
TQFP
14, 15
39
18
19
20
21
22
23
24
25
P3.0–P3.7
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
XTAL2,
XTAL1
A8 (P2.0)
A9 (P2.1)
NAME
GND
Port 3 (I/O). Port 3 functions as both an 8-bit bidirectional I/O port
and an alternate functional interface for external Interrupts, Serial
Port 0, Timer 0 and 1 Inputs, RD and WR strobes. The reset
condition of Port 3 is with all bits at logic 1. In this state, a weak
pullup holds the port high. This condition also serves as an input
mode, since any external circuit that writes to the port will overcome
the weak pullup. When software writes a 0 to any port pin, the
DS80C310 will activate a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has
been at 0 will cause a strong transition driver to turn on, followed by
a weaker sustaining pullup. Once the momentary strong driver turns
off, the port once again becomes both the output high and input
state. The alternate modes of Port 3 are as follows:
Crystal Oscillator Pins. XTAL1 and XTAL2 provide support for
parallel resonant, AT-cut crystals. XTAL1 also acts as an input in
the event that an external clock source is used in place of a crystal.
XTAL2 serves as the output of the crystal amplifier.
Digital Circuit Ground
Address Outputs (Port 2) (Output). Port 2 serves as the MSB for
external addressing. P2.7 is A15 and P2.0 is A8. The DS80C310
automatically places the MSB of an address on P2 for external ROM
and RAM access. Although Port 2 can be accessed like an ordinary
I/O port, the value stored on the Port 2 latch is never seen on the pins
(due to memory access). Therefore, writing to Port 2 in software is
only useful for the instructions MOVX A, @ Ri or MOVX @ Ri, A.
These instructions use the Port 2 internal latch to supply the external
address MSB; the Port 2 latch value is supplied as the address
information.
PDIP
10
11
12
13
14
15
16
17
4 of 24
PLCC
PIN
11
13
14
15
16
17
18
19
TQFP
10
11
12
13
5
7
8
9
PORT
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
FUNCTION
ALTERNATE
RXD0
TXD0
INT0
INT1
WR
RD
T0
T1
Serial Port 0
Input
Serial Port 0
Output
External Interrupt
0
External Interrupt
1
Timer 0 External
Input
Timer 1 External
Input
External Data
Memory Write
Strobe
External Data
Memory Read
Strobe
FUNCTION
DS80C310

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