ISP1504CBSTM ST-Ericsson Inc, ISP1504CBSTM Datasheet - Page 37

• Manufacturer Part Number: ISP1504CBSTM
• Description: IC USB TXRX HS 32-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1504CBSTM

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1504CBS-T; ISP1504CBS-T

NXP Semiconductors
ISP1504A_ISP1504C_3
Product data sheet
Fig 16. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[7:0]
STP
NXT
DIR
DM
D
N 4
DATA
D
N 3
9.9 Preamble
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the
ISP1504 operates just as in full-speed mode, and sends all data with the full-speed rise
time and fall time. Whenever the link transmits a USB packet in preamble mode, the
ISP1504 will automatically send a preamble header at full-speed bit rate before sending
the link packet at low-speed bit rate. The ISP1504 will ensure a minimum gap of four
full-speed bit times between the last bit of the full-speed PRE PID and the first bit of the
low-speed packet SYNC. The ISP1504 will drive a J for at least one full-speed bit time
after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus.
An example transmit packet is shown in
In preamble mode, the ISP1504 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
RX end delay
N 1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 03 — 7 April 2008
link decision time (1 to 14 clocks)
IDLE
Figure
ISP1504A; ISP1504C
17.
ULPI HS USB OTG transceiver
(one to two clocks)
TXCMD
TX start delay
© NXP B.V. 2008. All rights reserved.
SYNC
D0
004aaa713
36 of 82
D1