ISP1302HN-T ST-Ericsson Inc, ISP1302HN-T Datasheet
ISP1302HN-T
Specifications of ISP1302HN-T
Related parts for ISP1302HN-T
ISP1302HN-T Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1302 Universal Serial Bus On-The-Go transceiver with carkit support Rev. 01 — 24 May 2007 1. General description The ISP1302 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device that supports USB Carkit Specification (CEA-936-A), November 2005 . It ...
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... I Personal digital assistant 4. Ordering information Table 1. Ordering information Type number Package Name Description ISP1302HN HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 ISP1302UK WLCSP25 wafer level chip-size package; 25 bumps; 2.5 ISP1302_1 Product data sheet 4 0.85 mm Rev. 01 — 24 May 2007 ...
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... Rev. 01 — 24 May 2007 ISP1302 USB OTG transceiver with carkit support C_A C_B BUS CPGND CHARGE PUMP V 19 BUS V COMPARATOR BUS 18 ID DETECTOR ID 6 CR_INT ISP1302HN PULL-UP AND PULL-DOWN RESISTORS 10 SPKR_L AUDIO BYPASS 11 SPKR_R/MIC 004aaa541 2. © NXP B.V. 2007. All rights reserved ...
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... USB OTG transceiver with carkit support terminal 1 index area 1 ADR/PSW SDA 2 SCL 3 ISP1302HN 4 RESET_N INT_N 5 CR_INT 6 Transparent top view 6 CR_INT DGND INT_N 5 (exposed die pad) RESET_N 4 ISP1302HN 3 SCL terminal 1 SDA 2 ADR/PSW 1 terminal 1 index area Bottom view Rev. 01 — 24 May 2007 ISP1302 AGND DAT/VP 13 SE0/VM ...
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NXP Semiconductors Fig 4. Pin configuration WLCSP25 (top view) Fig 5. Pin configuration WLCSP25 (bottom view) 6.2 Pin description Table 2. Pin description [1] Symbol Pin Ball HVQFN24 WLCSP25 ADR/PSW 1 C1 SDA 2 D2 SCL 3 D3 RESET_N 4 ...
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NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin Ball HVQFN24 WLCSP25 CR_INT 6 C4 VREG 7 A2 SERVICE_N 8 A1 OE_N/INT_N 9 B3 SPKR_L 10 A3 SPKR_R/MIC 11 A4 RCV 12 A5 SE0/ DAT/ ...
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NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin Ball HVQFN24 WLCSP25 BUS C_A 21 E3 C_B 22 E2 CPGND CC(I/O) DGND exposed B2 ...
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NXP Semiconductors 7. Functional description 7.1 Serial controller The serial controller includes the following functions: • Serial controller interface • Device identification registers • Control registers • Interrupt registers • Interrupt generator The serial controller acts communicate ...
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NXP Semiconductors 7.4 ID detector In normal power mode (when both V the condition of the ID line and can differentiate between the following conditions: • The ID pin is floating (bit ID_FLOAT = 1). • The ID pin is ...
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NXP Semiconductors Table 4. ID_PULLDN PH_ID_ACK PH_ID_INT Switch between ID and ground 7.5 Pull-up and pull-down resistors Figure 6 connected to the DP and DM lines. The DP pull-up resistor (SW1) is controlled by bit ...
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NXP Semiconductors DP DM Fig 6. DP and DM pull-up and pull-down resistors 7.6 3.3 V DC-DC regulator The built-in DC-DC regulator conditions the input power supply (V the ISP1302. When V When V automatically bypassed so that pin VREG ...
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NXP Semiconductors 7.8 Audio bypass The audio bypass block includes audio switches and DC bias circuits, see Audio switches provide a low impedance path for analog audio signals from the phone processor to be routed to the DP and DM ...
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NXP Semiconductors SE0/VM DAT/VP Fig 8. Audio data control 7.9.1 Audio timer The audio timer has two main functions. The first function is to generate the timing for the positive and negative interrupt pulses. The second function is to generate ...
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NXP Semiconductors 7.9.3 Stereo interrupt detector The stereo interrupt detector generates an interrupt when the CR_INT pin has been continuously below the carkit interrupt detector threshold for a time 100 ms); refer to USB Carkit Specification (CEA-936-A), ...
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NXP Semiconductors Table 5. Pin RESET_N HIGH HIGH HIGH HIGH LOW [1] Include the internal power-on-reset pulse (active HIGH). Table 6 Table 6. USB mode DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 VP_VM VP_VM VP_VM VP_VM 7.11.2 Differential receiver The operation of the ...
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NXP Semiconductors Table 8. USB functional mode: receive operation USB mode Bit SUSPEND DAT_SE0 1 DAT_SE0 1 DAT_SE0 1 VP_VM 0 VP_VM 0 VP_VM 0 VP_VM 0 VP_VM 1 VP_VM 1 VP_VM 1 VP_VM 1 7.12 Power-On Reset (POR) When ...
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NXP Semiconductors The first function of the ADR/PSW pin is to set the I the RESET_N pin, the level on ADR/PSW is latched and stored in ADR_REG, which represents the Least Significant Bit (LSB) of the C-bus ...
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NXP Semiconductors 8. Modes of operation The ISP1302 supports three types of modes: • Power modes • USB modes • Transparent modes 8.1 Power modes 8.1.1 Normal mode In this mode, both V operation range. There are three levels of ...
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NXP Semiconductors Table 11. ISP1302 pin states in disable and isolate modes Pin name V , VREG CC V CC(I/ RCV RESET_N, SDA, SCL, ADR/PSW, SE0/VM, DAT/VP, INT_N, OE_N/INT_N, SERVICE_N SPKR_R/MIC, SPKR_L, ID, V BUS CR_INT, C_A, C_B ...
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NXP Semiconductors 8.3 Transparent modes 8.3.1 Transparent UART mode When in transparent UART mode, an SoC (with the UART controller) communicates through the ISP1302 to another UART device that is connected to its DP and DM lines. The ISP1302 operates ...
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NXP Semiconductors Table 13. Summary of device operating modes Mode Bit UART_EN USB mode 0 Transparent general-purpose 0 buffer mode Transparent audio mode 0 Transparent UART mode 1 Table 14. Bit TRANSP_BDIR[1: ISP1302_1 Product data sheet ...
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NXP Semiconductors 9. Serial controller 9.1 Register map Table 15 Table 15. Register overview Register Width (bits) Vendor ID 16 Product ID 16 Version ID 16 Mode Control 1 8 Mode Control 2 8 Audio Control 8 OTG Control 8 ...
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NXP Semiconductors Table 16. Vendor ID register (address R = 00h to 01h) bit description Bit Symbol VENDORID[15:0] 9.1.1.2 Product ID register The bit description of the Product ID register is given in Table 17. Product ID ...
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NXP Semiconductors Table 20. Mode Control 1 register (address S = 04h 05h) bit allocation Bit 7 Symbol reserved UART_EN Reset 0 0/1 Access R/S/C R/S/C Table 21. Bit Symbol UART_EN 5 OE_INT_EN 4 BDIS_ACON_ ...
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NXP Semiconductors Table 23. Bit 9.1.2.3 Audio Control register Table 24 Table 24. Audio Control register (address S = 16h 17h) bit allocation Bit 7 Symbol PH_ID_ PH_ID_INT ...
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NXP Semiconductors Table 27. Bit 9.1.2.5 Misc Control register Table 28 Table 28. Misc Control register (address S = 18h 19h) bit allocation Bit 7 Symbol FORCE_ FORCE_ DP_HIGH DP_LOW ...
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NXP Semiconductors Table 29. Bit 9.1.2.6 Carkit Control register Table 30 Table 30. Carkit Control register (address S = 1Ah 1Bh) bit allocation Bit 7 Symbol reserved Reset 0 Access R/S/C R/S/C Table ...
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NXP Semiconductors 9.1.2.7 Transmit Positive Width register This register specifies the width of the positive pulse, that is, the output on the DM line when the TX_PULSE_EN bit is set. The time is measured in units of 60 MHz clock ...
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NXP Semiconductors Table 37. Bit 9.1.3 Interrupt registers 9.1.3.1 Interrupt Source register Table 38 signals that can generate an interrupt. Table 38. Interrupt Source register (address R = 08h) bit allocation ...
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NXP Semiconductors Table 39. Bit Symbol 7 DP_INT 6 BDIS_ACON 5 ID_FLOAT 4 DM_HI 3 ID_GND 2 DP_HI 1 SESS_VLD 0 VBUS_VLD ISP1302_1 Product data sheet Interrupt Source register (address R = 08h) bit description Description This bit has two ...
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NXP Semiconductors 9.1.3.2 Interrupt Latch register This register indicates the source that generates an interrupt. For the bit allocation, see Table 40. Table 40. Interrupt Latch register (address S = 0Ah 0Bh) bit allocation Bit 7 Symbol DP_INT_ ...
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NXP Semiconductors Table 43. Bit 9.1.3.4 Interrupt Enable High register The bits in this register enable interrupts when the corresponding bits in the Interrupt Source register change from logic 0 to logic ...
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NXP Semiconductors Table 45. Bit 9.2 Interrupts Any of the Interrupt Source register signals given in when the signal becomes either LOW or HIGH. After an interrupt is generated, the SoC should be able to read the ...
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NXP Semiconductors Table 48. Bit 9.3.3 Write format A write operation can be performed as: • One-byte write to the specified register address. • Multiple-byte write to N consecutive registers, starting from the specified start address. ...
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NXP Semiconductors Table 50. Byte ACK : Write data ACK P Figure 11 S device select S device select write data Fig 11. Writing data to the ISP1302 registers 9.3.4 Read format A read ...
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NXP Semiconductors Table 51. Byte S Device select ACK Read data K No ACK P Fig 12. Current address read 9.3.4.2 Random address read: single read Table 52 sequence. Table 52. SDA line S Device select ACK Register address K ...
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NXP Semiconductors Table 53. SDA line ACK S Device select ACK Read data K ACK Read data ACK : Read data ACK P S device select wr S device select wr read data ...
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NXP Semiconductors 10.2 Clock wake-up event The clock wakes up when any of the following events occurs on the ISP1302 pins: • Pin SCL goes LOW. • Pin V Interrupt Enable High register is set. • Status bit ID_FLOAT changes ...
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NXP Semiconductors 11. Limiting values Table 54. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Voltage V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V input voltage on pin ...
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NXP Semiconductors Table 55. Recommended operating conditions Symbol Parameter V input voltage I V open-drain pull-up voltage (pu)OD Temperature T ambient temperature amb [1] V should be less than or equal to V CC(I/O) 13. Static characteristics Table 56. Static ...
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NXP Semiconductors Table 57. Static characteristics: digital pins CC(I/O) Typical values are 3 Symbol Parameter Input level voltage ...
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NXP Semiconductors Table 58. Static characteristics: analog I/O pins DP and CC(I/O) Typical values are 3 Symbol ...
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NXP Semiconductors Table 60. Static characteristics: charge pump CC(I/O) Typical values are 3 Symbol Parameter V B-device session ...
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NXP Semiconductors 14. Dynamic characteristics Table 62. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 Symbol ...
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NXP Semiconductors Table 65. Dynamic characteristics: analog I/O pins DP and CC(I/O) otherwise specified. Typical values are 3 ...
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NXP Semiconductors Table 66. Dynamic characteristics: analog I/O pin CC(I/O) otherwise specified. Typical values are 3 Symbol ...
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NXP Semiconductors Fig 14. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL V OH differential V CRS data ...
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NXP Semiconductors Fig 19. Load on pins DP and DM Fig 20. Load on pins DP and DM for enable time and disable time Fig 21. Load on pins SE0/VM, DAT/VP and RCV 14.1 Test configurations Table 68. Parameter Termination ...
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NXP Semiconductors Fig 22. V 14.2 Audio crosstalk test conditions V sweeps from 2 4.2 V (DC waveform). CC 14.2.1 Test 1 • SW2 = on and SW3 = on. • terminated using a 200 • ...
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NXP Semiconductors 2 14.4 I C-bus characteristics SDA LOW SCL t HD;STA t HD;DAT S Fig 23. Definition of timing for standard mode or fast mode devices on the I Table 69. Characteristics of I/O ...
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... The figure shows the HVQFN pinout. For the WLCSP ballout, see Fig 24. Application diagram V CC(I/ SW1 SW- C10 0 ADR/PSW CC(I/ SDA CPGND 2 23 C_B SCL 3 22 C_A RESET_N INT_N CR_INT BUS ISP1302HN 6 19 VREG SERVICE_N AGND OE_N/INT_N 9 16 SPKR_L SPKR_R/MIC DAT/ RCV SE0/ DGND 0.1 F Table CC(I/ 0.1 F SHIELD ...
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NXP Semiconductors 16. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area ...
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NXP Semiconductors WLCSP25: wafer level chip-size package; 25 bumps; 2.5 x 2.5 x 0.6 mm bump A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.26 ...
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NXP Semiconductors 17. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering ...
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NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Additional soldering information A more in-depth account of soldering WLCSP (Wafer-Level ...
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NXP Semiconductors Table 72. Acronym SRP TxD UART USB WLCSP 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB Specification Rev. 1.2 [3] On-The-Go Transceiver Specification (CEA-2011) [4] USB Carkit Specification (CEA-936-A), November 2005 ...
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NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors Table 59. Static characteristics: analog I/O pin .42 Table 60. Static characteristics: charge pump . . . . . . . . .42 Table 61. Static characteristics: analog I/O pins SPKR_R/MIC and ...
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NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration ...
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NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17.1 Introduction to soldering . . ...