PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 333

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-I/SO

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

21.4.17.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its inactive state
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘ 1 ’ during the Start condition.
FIGURE 21-28:
 2011 Microchip Technology Inc.
(Figure
SDA
SCL
SEN
BCLIF
S
SSPIF
SDA or SCL is sampled low at the beginning of
the Start condition
SCL is sampled low before SDA is asserted low
(Figure
21-28)
21-29).
Bus Collision During a Start
Condition
condition if SDA = 1, SCL = 1
Set SEN, enable Start
BUS COLLISION DURING START CONDITION (SDA ONLY)
(Figure
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
21-28).
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SDA = 0, SCL = 1.
Set BCLIF,
Preliminary
SSPIF and BCLIF are
cleared in software
PIC18F66K80 FAMILY
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0. If the SCL pin is sampled as ‘ 0 ’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
21-30). If, however, a ‘ 1 ’ is sampled on the SDA
The reason that bus collision is not a fac-
tor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPIF and BCLIF are
cleared in software
DS39977C-page 333