PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 340

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-I/SO

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
22.1
The operation of each Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
These are detailed on the following pages in
Register
respectively.
REGISTER 22-1:
DS39977C-page 340
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-x
CSRC
EUSART Control Registers
22-1,
SREN/CREN overrides TXEN in Sync mode.
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit is enabled
0 = Transmit is disabled
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
TRMT: Transmit Shift Register Status bit
1 = TSR is empty
0 = TSR is full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Register 22-2
R/W-x
TX9
TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
TXEN
and
R/W-x
(1)
Register
(1)
R/W-x
SYNC
22-3,
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SENDB
R/W-x
Note:
Throughout this section, references to
register and bit names that may be asso-
ciated with a specific EUSART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive
EUSART1 or EUSART2.
BRGH
R/W-x
Status
 2011 Microchip Technology Inc.
x = Bit is unknown
TRMT
R-x
register
for
R/W-x
TX9D
either
bit 0