PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 502

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-I/SO

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
BZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39977C-page 502
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Zero
BZ
-128  n  127
if Zero bit is ‘ 1 ’,
(PC) + 2 + 2n  PC
None
If the Zero bit is ‘ 1 ’, then the program
will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
1 ;
address (Jump)
0 ;
address (HERE + 2)
0000
operation
BZ
Process
Process
Data
Data
No
Q3
Q3
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn
Preliminary
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PC
TOS
WS
BSRS
STATUSS =
No
Q1
Read literal
=
=
=
=
=
operation
‘k’<7:0>,
Subroutine Call
CALL k {,s}
0  k  1048575
s  [0,1]
(PC) + 4  TOS,
k  PC<20:1>;
if s = 1
(W)  WS,
(STATUS)  STATUSS,
(BSR)  BSRS
None
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC+ 4) is pushed onto the return stack.
If ‘s’ = 1 , the W, STATUS and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0 , no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
2
2
HERE
1110
1111
No
Q2
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
STATUS
 2011 Microchip Technology Inc.
k
110s
CALL
Push PC to
19
operation
kkk
stack
No
Q3
THERE,1
k
kkkk
7
kkk
Read literal
Write to PC
’k’<19:8>,
operation
No
Q4
kkkk
kkkk
0
8