PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 68

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-I/SO

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
4.1.3
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable. The HF-
INTOSC and MF-INTOSC are termed as INTOSC in
this chapter.
Three bits indicate the current clock source and its
status, as shown in
• OSTS (OSCCON<3>)
• HFIOFS (OSCCON<2>)
• SOSCRUN (OSCCON2<6>)
TABLE 4-2:
When the OSTS bit is set, the primary clock is providing
the device clock. When the HFIOFS or MFIOFS bit is
set, the INTOSC output is providing a stable clock
source to a divider that actually drives the device clock.
When the SOSCRUN bit is set, the SOSC oscillator is
providing the clock. If none of these bits are set, either
the LF-INTOSC clock source is clocking the device or
the INTOSC source is not yet stable.
If the internal oscillator block is configured as the
primary clock source by the FOSC<3:0> Configuration
bits (CONFIG1H<3:0>). Then, the OSTS and HFIOFS
or MFIOFS bits can be set when in PRI_RUN or
PRI_IDLE mode. This indicates that the primary clock
(INTOSC output) is generating a stable output. Enter-
ing another INTOSC power-managed mode at the
same frequency would clear the OSTS bit.
DS39977C-page 68
Primary Oscillator
INTOSC (HF-INTOSC
or MF-INTOSC)
Secondary Oscillator
MF-INTOSC or
HF-INTOSC as
Primary Clock Source
LF-INTOSC is
Running or INTOSC is
not yet Stable
Main Clock Source
Note 1: Caution should be used when modifying
2: Executing a SLEEP instruction does not
CLOCK TRANSITIONS AND STATUS
INDICATORS
a single IRCF bit. At a lower V
possible to select a higher clock speed
than is supportable by that V
device operation may result if the V
F
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
OSC
SYSTEM CLOCK INDICATOR
specifications are violated.
Table
OSTS
4-2. The three bits are:
1
0
0
1
0
HFIOFS or
MFIOFS
0
1
0
1
0
DD
SOSCRUN
. Improper
DD
0
0
1
0
0
, it is
DD
Preliminary
/
4.1.4
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
4.2
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled. (For details, see
Start-up”.) In this mode, the OSTS bit is set. The
HFIOFS or MFIOFS bit may be set if the internal
oscillator block is the primary clock source. (See
Section 3.2 “Control
4.2.2
The SEC_RUN mode is the compatible mode to the
“clock-switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the SOSC oscillator. This enables lower
power consumption while retaining a high-accuracy
clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
SOSC oscillator (see
is shut down, the SOSCRUN bit (OSCCON2<6>) is set
and the OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the SOSC oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure
SOSCRUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up and the
SOSC oscillator continues to run.
Note:
4-2). When the clock switch is complete, the
Run Modes
MULTIPLE SLEEP COMMANDS
PRI_RUN MODE
SEC_RUN MODE
The SOSC oscillator can be enabled by
setting the SOSCGO bit (OSCCON2<3>).
If this bit is set, the clock switch to the
SEC_RUN mode can switch immediately
once SCS<1:0> are set to ‘01’.
Figure
Registers”.)
 2011 Microchip Technology Inc.
Section 28.4 “Two-Speed
4-1), the primary oscillator