ICS1893Y-10T IDT, Integrated Device Technology Inc, ICS1893Y-10T Datasheet - Page 93
ICS1893Y-10T
Manufacturer Part Number
ICS1893Y-10T
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Datasheet
1.ICS1893Y-10.pdf
(150 pages)
Specifications of ICS1893Y-10T
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Other names
1893Y-10T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893Y-10T
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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7.12.1 Data Rate (bit 17.15)
7.12.2 Duplex (bit 17.14)
7.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11)
ICS1893Y-10 Rev F 1/20/04
The Data Rate bit indicates the ‘selected technology’. If the ICS1893Y-10 is in:
•
•
When bit 17.15 is logic:
•
•
Note:
The Duplex bit indicates the ‘selected technology’. If the ICS1893Y-10 is in:
•
•
When bit 17.14 is logic:
•
•
Note:
The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the
three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually
examines the state of the Auto-Negotiation Process State Machine and reports the status of
Auto-Negotiation using the three Auto-Negotiation Monitor bits. Therefore, the value of these three bits
provides the status of the Auto-Negotiation Process.
These three bits are initialized to logic zero in one of the following ways:
•
•
•
Hardware mode, the value of this bit is determined by the 10/100SEL input pin.
Software mode, the value of this bit is determined by the Data Rate bit 0.13.
Zero, it indicates that 10-MHz operations are selected.
One, the ICS1893Y-10 is indicating that 100-MHz operations are selected.
Hardware mode, the value of this bit is determined by the DPXSEL input pin.
Software mode, the value of this bit is determined by the Duplex Mode bit 0.8.
Zero, it indicates that half-duplex operations are selected.
One, the ICS1893Y-10 is indicating that full-duplex operations are selected.
A reset (see
Disabling Auto-Negotiation [see
Restarting Auto-Negotiation [see
ICS1893Y-10 - Release
This bit does not imply any link status.
This bit does not imply any link status.
Section 4.1, “Reset
Copyright © 2004, Integrated Circuit Systems, Inc.
Section 7.2.4, “Auto-Negotiation Enable (bit
Operations”)
Section 7.2.7, “Restart Auto-Negotiation (bit
All rights reserved.
93
Chapter 7 Management Register Set
0.12)”]
0.9)”]
January, 2004
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