IDT82P2282PF8 IDT, Integrated Device Technology Inc, IDT82P2282PF8 Datasheet - Page 117

• Manufacturer Part Number: IDT82P2282PF8
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF8

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF8

5.1.1.2
PMON
RCRB
RPLC
TPLC
Programming Information
IDT82P2282
Address (Hex)
Address (Hex)
Address (Hex)
Address (Hex)
01 ~ 18
21 ~ 38
41 ~ 58
01 ~ 18
01 ~ 18
21 ~ 38
41 ~ 58
0A
0B
00
01
02
03
04
05
06
07
08
09
Indirect Register
SUBST2
PRGD15
SUBST2 SUBST1
CRCE7
PRGD7
DTRK7
DDSE7
DTRK7
LCV15
FER7
LCV7
Bit 7
Bit 7
Bit 7
Bit 7
-
-
-
-
-
-
-
-
SUBST1
PRGD14
PRGD6
DTRK6
DTRK6
CRCE6
DDSE6
Bit 6
LCV14
TEST
TEST
FER6
LCV6
Bit 6
Bit 6
Bit 6
-
-
-
-
-
-
SUBST0
Bit 5
SUBST0
PRGD13
DTRK5
SIGINS
DTRK5
CRCE5
PRGD5
DDSE5
LCV13
Bit 5
FER5
LCV5
-
Bit 5
Bit 5
-
-
-
-
-
-
EXTRACT
STRKEN
STRKEN
Bit 4
DTRK4
DTRK4
PRGD12
SINV
Bit 4
CRCE4
PRGD4
DDSE4
SINV
LCV12
Bit 4
OOF4
FER4
LCV4
Bit 4
-
-
-
-
DTRK3
Bit 3
DTRK3
OINV
Bit 3
OINV
Bit 3
PRGD11
A
CRCE3
PRGD3
DDSE3
FER11
LCV11
A
OOF3
A
FER3
LCV3
Bit 3
-
-
-
Bit 2
DTRK2
DTRK2
EINV
EINV
B
Bit 2
Bit 2
117
PRGD10
B
B
PRGD2
CRCE2
DDSE2
COFA2
FER10
LCV10
OOF2
FER2
LCV2
Bit 2
-
-
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Bit 1
DTRK1
DTRK1
G56K
C
G56K
Bit 1
Bit 1
C
C
CRCE1
CRCE9
PRGD1
PRGD9
COFA1
DDSE1
DDSE9
OOF1
FER1
FER9
LCV1
LCV9
Bit 1
Bit 0
DTRK0
DTRK0
D
Bit 0
GAP
Bit 0
GAP
D
D
CRCE0
CRCE8
PRGD0
PRGD8
COFA0
DDSE0
DDSE8
OOF0
FER0
FER8
LCV0
LCV8
Bit 0
Extracted Signaling Data/Extract
Enable Register for CH1 ~ CH24
Signaling Trunk Conditioning Code
Channel Control Register for CH1
Channel Control Register for CH1
Code Register for CH1 ~ CH24
Data Trunk Conditioning Code
Data Trunk Conditioning Code
Signaling Trunk Conditioning
Register for CH1 ~ CH24
Register for CH1 ~ CH24
Register for CH1 ~ CH24
PRGD Counter Mapping 0
CRCE Counter Mapping 0
CRCE Counter Mapping 1
PRGD Counter Mapping 1
DDSE Counter Mapping 0
DDSE Counter Mapping 1
FER Counter Mapping 0
FER Counter Mapping 1
LCV Counter Mapping 0
LCV Counter Mapping 1
COFA Counter Mapping
OOF Counter Mapping
Register
Register
Register
~ CH24
~ CH24
Register
August 20, 2009
Reference Page
Reference Page
Reference Page
Reference Page
P 233
P 237
P 238
P 239
P 227
P 227
P 228
P 228
P 229
P 229
P 230
P 230
P 231
P 231
P 232
P 232
P 234
P 235
P 236