IDT82P2282PFG IDT, Integrated Device Technology Inc, IDT82P2282PFG Datasheet - Page 352
IDT82P2282PFG
Manufacturer Part Number
IDT82P2282PFG
Description
TXRX T1/J1/E1 2CHAN 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2282PF8.pdf
(381 pages)
Specifications of IDT82P2282PFG
Number Of Drivers/receivers
2/2
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82P2282PFG
Available stocks
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HITACHI
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G56K, GAP:
E1 Data Trunk Conditioning Code Register (20H ~ 3FH)
DTRK[7:0]:
SUBST[2:0] bits (b7~5, E1-ID-00~1FH).
Programming Information
IDT82P2282
Bit Name
Default
Bit No.
Type
These bits are valid in Receive Clock Master mode when the PCCE bit (b0, E1-0D1H,...) is ‘1’.
These bits are the data trunk codes that can replace the data of the timeslot selected by the GSUBST[2:0] bits (b2~0, E1-0D0H,...) or the
DTRK7
R/W
7
0
G56K
X
0
1
DTRK6
GAP
R/W
0
0
1
6
0
The corresponding timeslot is not gapped.
Bit 8 (LSB) of the corresponding timeslot is gapped (no clock signal during the Bit 8).
The corresponding timeslot is gapped (no clock signal during the timeslot).
DTRK5
R/W
5
0
DTRK4
R/W
4
0
352
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Gap Mode
DTRK3
R/W
3
0
DTRK2
R/W
2
0
DTRK1
R/W
1
0
August 20, 2009
DTRK0
R/W
0
0
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