UBA2032TS/N2/N,118 NXP Semiconductors, UBA2032TS/N2/N,118 Datasheet - Page 19

• Manufacturer Part Number: UBA2032TS/N2/N,118
• Description: MOSFET & Power Driver ICs Full Bridg Driver IC
• Manufacturer: NXP Semiconductors

Specifications of UBA2032TS/N2/N,118

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935278859118

NXP Semiconductors
UJA1079_2
Product data sheet
6.6.1 Battery pin (BAT)
6.6.2 Voltage regulator V1
6.6 Power supplies
The SBC contains a single supply pin, BAT. An external diode is needed in series to
protect the device against negative voltages. The operating range is from 4.5 V to 28 V.
The SBC can handle maximum voltages up to 40 V.
If the voltage on pin BAT falls below the power-off detection threshold, V
immediately enters Off mode, which means that the voltage regulator and the internal
logic are shut down. The SBC leaves Off mode for Standby mode as soon as the voltage
rises above the power-on detection threshold, V
register is set to 1 when the SBC leaves Off mode.
Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional
transceivers. V1 is supplied by pin BAT and delivers up to 250 mA at 3.3 V or 5 V
(depending on the UJA1079 version).
To prevent the device overheating at high ambient temperatures or high average currents,
an external PNP transistor can be connected as illustrated in
configuration, the power dissipation is distributed between the SBC and the PNP
transistor. Bit PDC in the Mode_Control register
power dissipation is distributed − if PDC = 0, the PNP transistor will be activated when the
load current reaches 85 mA (50 mA if PDC = 1) at T
85 mA while the transistor delivers the additional load current (see
Fig 6.
External PNP transistor control circuit
battery
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
BAT
UJA107x
VEXCTRL
th(det)pon
(Table
vj
= 150 °C. V1 will continue to deliver
015aaa098
VEXCC
5) is used to regulate how the
. The POSI bit in the Int_Status
V1
LIN core system basis chip
Figure
Figure 7
6. In this
UJA1079
© NXP B.V. 2010. All rights reserved.
th(det)poff
and
Figure
, the SBC
19 of 45
8).