PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 253

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.3.19
Value after reset: (not defined)
RHCRD
In all modes except transparent modes 2 and 3, this register contains the control field of
a received HDLC-frame. In transparent modes 2 and 3, the register is not used.
Mode
Auto-mode, 1-byte
address (U/I frames)
Auto-mode, 2-byte
address (U/I frames)
Auto-mode, 1-byte
address (I frames)
Auto-mode, 2-byte
address (I frames)
Non-auto-mode,
1-byte address
Non-auto-mode,
2-byte address
Transparent mode 1
Transparent mode 2
Transparent mode 3
1)
2)
3)
4)
S-frames are handled automatically and are not transferred to the microprocessor.
For U-frames (bit 0 of RHCRD = 1) the control field is as: in the modulo 8 case.
I-field.
For I-frames (bit 0 of RHCRD = 0) the compressed control field has the same format as in the modulo 8 case,
but only the three LSB’s of the receive and transmit counters are visible:
7
N(R)
RHCRD - Receive HDLC Control Register for D-Channel (Read)
7
1)
1)
2-0
Modulo 8
(MCS=0)
Control field
Control field
2
3
3
–
–
nd
rd
rd
byte after flag
byte after flag
byte after flag
Contents of RHCRD
P
N(S)
253
Modulo 128
(MCS=1)
U-frames only:
Control field
U-frames only:
Control field
Control field
compressed form
Control field in
compressed form
Detailed Register Description
2)
2)
2-0
4)
4)
0
Contents of RFIFOD
From 3
From 4
From 4
From 5
From 3
From 4
From 4
From 1
From 2
0
0
rd
th
th
th
rd
th
th
st
nd
byte after flag
byte after flag
byte after flag
byte after flag
byte after flag
byte after flag
byte after flag
byte after flag
byte after flag
PSB 2115
PSF 2115
11.97
(A9)
3)
3)
3)
3)