PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 258

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

BAS ... Bus Access Status
Indicates the state of the TIC-bus:
0: the IPAC itself occupies the D- and C/I-channel
1: another device occupies the D- and C/I-channel
CODR0 ... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
CIC1 ... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been
recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by
a read of CIR0.
CIC1 is only used if Terminal Mode is selected.
4.3.23
Value after reset: 7C
CIR0
Note: The BAS and CODR0 bits are updated every time a new C/I-code is detected in
Semiconductor Group
two consecutive IOM-frames. If several consecutive valid new codes are detected
and CIR0 is not read, only the first and the last C/I code (and BAS bit) is made
available in CIR0 at the first and second read of that register, respectively.
CIR0 - Command/Indication Receive 0 (Read)
7
0
BAS
H
CODR0
258
Detailed Register Description
CIC0
0
CIC1
PSB 2115
PSF 2115
11.97
(B1)