PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 88

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Functional Description
Figure 30
Receiver Thresholds
The peak detector requires maximum 2 s to reach the peak value while storing the peak
level for at least 250 s (RC > 1 ms).
The additional level detector for power up/down control works with fixed thresholds at
100 mV. The level detector monitors the line input signals to detect whether an INFO is
present. In TE and LT-T mode, when closing an analog loop, it is therefore possible to
indicate an incoming signal during activated loop. In LT-S analog loop-back mode the
level detector monitors its own loop signal and an incoming signal is not recognized.
2.5.3.2
Level Detection Power Down (TE mode)
If CONF:CFS is set to “0“, the clocks are also provided in power down state, whereas if
CFS is set to “1“, only an analog level detector is active in power down state. All clocks,
including the IOM interface, are stopped. The data lines are "high", whereas the clocks
are "low".
An activation initiated from the exchange side (Info 2 on S-bus detected) will have the
consequence that a clock signal is provided automatically.
From the terminal side an activation must be started by setting and resetting the SPU-
bit in the SPCR register and writing TIM to CIX0 or by resetting CFS=0.
Semiconductor Group
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11.97