PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 259

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.3.24
Value after reset: 3F
CIX0
RSS ... Reset Source Select
Only valid if the terminal specific functions are activated (STCR:TSF).
0
1
After a reset pulse generated by the IPAC and the corresponding interrupt (WOV, SAW
or CIC) the actual reset source can be read from the ISTAD and EXIRD-register.
Note: ’External Awake’ is only available in TE mode.
BAC ... Bus Access Control
Only valid if the TIC-bus feature is enabled (MODED:DIM2-0).
If this bit is set, the IPAC will try to access the TIC-bus to occupy the C/I-channel even if
no D-channel frame has to be transmitted. It should be reset when the access has been
completed to grant a similar access to other devices transmitting in that IOM-channel.
Note: Access is always granted by default to the IPAC with TIC-Bus Address (TBA2-0,
CODX0 ... C/I-Code 0 Transmit
Code to be transmitted in the C/I-channel / C/I-channel 0.
Subscriber or Exchange Awake
As reset source serves:
– a falling edge on the EAW-line (External Subscriber Awake)
– a C/I code change (Exchange Awake).
A logical zero on the EAW-line activates also the IOM-interface clock and frame
signal, just as the SPU-bit (SPCR) does.
Watchdog Timer
The expiration of the watchdog timer generates a reset pulse. The watchdog timer
will be reset and restarted, when two specific bit combinations are written in the
ADF1-register within the time period of 128 ms (see also ADF1 register
description).
STCR register) “7”, which has the lowest priority in a bus configuration.
CIX0 - Command/Indication Transmit 0 (Write)
7
RSS
BAC
H
CODX0
259
Detailed Register Description
1
0
1
PSB 2115
PSF 2115
11.97
(B1)