MT46V64M8BN-6:FTR Micron Technology Inc, MT46V64M8BN-6:FTR Datasheet - Page 76

• Manufacturer Part Number: MT46V64M8BN-6:FTR
• Manufacturer: Micron Technology Inc

Specifications of MT46V64M8BN-6:FTR

• Lead Free Status / Rohs Status: Compliant

Figure 40:
Figure 41:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Nonconsecutive WRITE-to-WRITE
Random WRITE Cycles
Notes:
Notes:
t DQSS (NOM)
1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
Command
1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
Address
Command
column g).
respectively.
Address
DQS
CK#
DM
DQ
CK
DQS
CK#
DM
DQ
CK
WRITE
Bank,
Col b
T0
WRITE
Bank,
Col b
T0
t DQSS (NOM)
t DQSS
WRITE
Bank,
Col x
DI
T1
b
NOP
DI
T1
b
76
T1n
DI
b'
T1n
WRITE
Bank,
Col n
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T2
DI
x
NOP
T2
T2n
DI
x'
512Mb: x4, x8, x16 DDR SDRAM
T2n
WRITE
Bank,
Col a
T3
DI
n
WRITE
Bank,
Col n
T3
Transitioning Data
T3n
DI
n'
Transitioning Data
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WRITE
Bank,
Col g
T4
DI
a
NOP
DI
T4
n
T4n
DI
a'
T4n
Operations
NOP
T5
DI
g
Don’t Care
T5
NOP
Don’t Care
T5n
DI
g'
T5n