STM32W108CBU63TR STMicroelectronics, STM32W108CBU63TR Datasheet - Page 37

• Manufacturer Part Number: STM32W108CBU63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
6.2.4
31
15
30
14
●
●
Table 3
Table 3.
Reset register
Reset event source register (RESET_EVENT)
Address offset: 0x4000 002C
Reset value: 0x0000 0001
Bit 7 CPU_LOCKUP: When set to ‘1’, the reset is due to core lockup.
Bit 6 OPT_BYTE_FAIL: When set to ‘1’, the reset is due to an Option byte load failure (may be set
Bit 5 WAKE_UP_DSLEEP: When set to ‘1’, the reset is due to a wake-up from Deep Sleep.
POR HV
POR LV (in deep sleep)
POR LV (not in deep
sleep)
RSTB
Watchdog reset
Software reset
Option byte error
Normal deep sleep
Emulated deep sleep
Debug reset
29
13
PRESETHV
PRESETLV
with other bits).
Reset source
shows which reset sources generate certain resets.
28
12
Reserved
Generated resets
27
11
26
10
PORESET
25
9
Peripheral reset for always-on power domain, for peripherals
that are required to retain their configuration across a deep
sleep cycle.
Peripheral reset for core power domain, for peripherals that
are not required to retain their configuration across a deep
sleep cycle.
Doc ID 16252 Rev 8
X
X
X
X
X
X
24
8
Reserved
CPU_L
SYSRESET
OCKU
23
P
7
r
X
X
X
X
X
X
X
X
X
X
OPT_B
YTE_F
AIL
22
6
r
Reset generation
WAKE_
UP_DS
DAPRESET
LEEP
21
5
r
X
X
X
X
SW_
RST
20
4
r
PRESETHV
DOG
W_
19
3
r
X
X
X
X
X
RSTB_
System modules
PIN
18
2
r
POWE
PRESETLV
R_LV
17
1
r
X
X
X
X
X
X
X
X
X
37/209
POWE
R_HV
16
0
r