STM32W108HBU64TR STMicroelectronics, STM32W108HBU64TR Datasheet - Page 43
STM32W108HBU64TR
Manufacturer Part Number
STM32W108HBU64TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32W108B-KEXT.pdf
(209 pages)
Specifications of STM32W108HBU64TR
Applications
RF4CE, Remote Control
Core Processor
ARM® Cortex-M3™
Program Memory Type
FLASH (128 kB)
Controller Series
STM32W
Ram Size
8K x 8
Interface
I²C, SPI, UART/USART
Number Of I /o
18
Voltage - Supply
1.18 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32W108HBU64TR
Manufacturer:
TDK
Quantity:
30 000
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STM32W108CB, STM32W108HB
6.4.3
6.4.4
31
15
31
15
30
14
30
14
Bits [15:0] WDOG_CTRL: Write 0xDEAD to disable or 0xEABE to enable.
Event timer
The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can
be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock.
FCLK is either the SCLK or PCLK as selected by CPU_CLK_SEL (see
switching on page
Slow timers (Watchdog and Sleeptimer) control and status registers
These registers are powered from the always-on power domain.
All registers are only writable when in System mode
Watchdog general control register (WDOG_CFG)
Register bits for general top level chip functions and protection.
Watchdog bits can only be written after first writing the appropriate code to the
WDOG_CTRL register.
Address:
Reset value:
Watchdog control register (WDOG_CTRL)
Requires magic number write to arm the watchdog enable or disable function.
Address:
Reset value:
Bit 1 WDOG_DIS: Watchdog disable
Bit 0 WDOG_EN: Watchdog enable
29
13
29
13
28
12
28
12
27
11
27
11
0x4000 6000
0x0000 0002
0x4000 6004
0x0000 0000
40).
26
10
26
10
25
25
9
9
Reserved
Doc ID 16252 Rev 8
24
24
WDOG_CTRL
8
8
Reserved
Reserved
w
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
Section 6.3.5: Clock
System modules
18
18
2
2
WDOG
_DIS
17
17
rw
1
1
43/209
WDOG
_EN
16
rw
16
0
0
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