MT46H8M32LFB5-6:A Micron Technology Inc, MT46H8M32LFB5-6:A Datasheet - Page 80
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MT46H8M32LFB5-6:A
Manufacturer Part Number
MT46H8M32LFB5-6:A
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H8M32LFB5-6A.pdf
(96 pages)
Specifications of MT46H8M32LFB5-6:A
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
6.5/5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
120mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46H8M32LFB5-6:A
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT46H8M32LFB5-6:A TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Command
Address
DQS
DQS
DQS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DM
DM
DM
DQ
DQ
DQ
CK#
5, 6
5, 6
5, 6
CK
1
7
6
7
6
7
6
WRITE
Bank a,
Col b
T0
Notes:
2
t
t
t
DQSS
DQSS
DQSS
1. An interrupted burst of 8 is shown; one data element is written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4.
5. DQS is required at T4 and T4n to register DM.
6. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. D
D
IN
t
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
D
IN
T1
IN
b = data-in for column b.
D
IN
T1n
NOP
T2
T2n
80
T3
NOP
256Mb: x16, x32 Mobile LPDDR SDRAM
t
WR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3n
4
NOP
T4
Don’t Care
T4n
(a or all)
T5
PRE
Bank
©2008 Micron Technology, Inc. All rights reserved.
3
WRITE Operation
Transitioning Data
T6
NOP