ICS87321AMILF IDT, Integrated Device Technology Inc, ICS87321AMILF Datasheet - Page 9

• Manufacturer Part Number: ICS87321AMILF
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS87321AMILF

• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: SOIC N
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
F
F
IDT
F
IGURE
PP
IGURE
IGURE
IFFERENTIAL
ICS87321I
÷1, ÷2 DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
™
and V
3.3V
R5,R6 locate near the driver pin.
/ ICS
3.3V
LVPECL
2C. H
2A. H
2E. H
1.8V
™
CMR
LVPECL
3.3V LVPECL CLOCK GENERATOR
R5
100 - 200
input requirements. Figures 2A to 2E show interface
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V LVPECL D
IDT H
3.3V LVPECL D
I
I
I
P
P
P
C
ER
ER
ER
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
R6
100 - 200
Zo = 50 Ohm
Zo = 50 Ohm
C
C
I
C
P
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
ER
C
I
NPUT
LOCK
S CLK/nCLK I
S CLK/nCLK I
S CLK/nCLK I
RIVER
S LVHSTL D
RIVER WITH
R1
50
3.3V
R3
125
C1
C2
I
NTERFACE
R1
84
R2
50
3.3V
R3
125
SWING
R4
125
R1
84
R2
84
and V
CLK
nCLK
R4
125
NPUT
R2
84
AC C
NPUT
CLK
nCLK
NPUT
3.3V
3.3V
RIVER
HiPerClockS
Input
OH
HiPerClockS
Input
D
D
D
OUPLE
CLK
nCLK
must meet the
RIVEN BY
RIVEN BY
RIVEN BY
3.3V
HiPerClockS
Input
9
F
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
F
IGURE
IGURE
3.3V
3.3V
2D. H
2B. H
LVDS_Driv er
LVPECL
3.3V LVDS D
3.3V LVPECL D
I
I
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
C
C
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
S CLK/nCLK I
S CLK/nCLK I
RIVER
R1
50
RIVER
R3
50
ICS87321AMI REV. A APRIL 7, 2009
R2
50
R1
100
CLK
nCLK
3.3V
NPUT
NPUT
HiPerClockS
Input
CLK
nCLK
D
D
3.3V
RIVEN BY
RIVEN BY
Receiv er