DS26528G+ Maxim Integrated Products, DS26528G+ Datasheet - Page 158

• Manufacturer Part Number: DS26528G+
• Description: IC TXRX T1/E1/J1 OCT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26528G+

• Number Of Drivers/receivers: 4/4
• Protocol: IEEE 1149.1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. See
Bit 6: CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error.
Bit 5: CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are
received in error.
Bit 4: FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.
Bit 3: Receive-Signaling All-Ones Event (RSA1). Set when the contents of time slot 16 contains fewer than three
zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
Bit 2: Receive-Signaling All-Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros.
Bit 1: Receive CRC-4 Multiframe Event (RCMF). Set on CRC-4 multiframe boundaries. This bit continues to be
set every 2ms on an arbitrary boundary if CRC-4 is disabled.
Bit 0: Receive Align Frame Event (RAF). Set approximately every 250μs to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
—
7
0
RLS2 (E1 Mode)
Receive Latched Status Register 2
091h + (200h x n): where n = 0 to 7, for Ports 1 to 8
CRCRC
6
0
CASRC
5
0
FASRC
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4
0
RSA1
3
0
DS26528 Octal T1/E1/J1 Transceiver
RSA0
2
0
RCMF
1
0
RLS2
for T1 mode.
RAF
0
0