DS26528G+ Maxim Integrated Products, DS26528G+ Datasheet - Page 166

• Manufacturer Part Number: DS26528G+
• Description: IC TXRX T1/E1/J1 OCT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26528G+

• Number Of Drivers/receivers: 4/4
• Protocol: IEEE 1149.1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
* RLS6 is reserved for future use.
** Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode.
The Receive Interrupt Information register (RIIR) indicates which of the DS26528 status registers are generating an
interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the receive status registers
is (are) causing the interrupt(s). The RIIR bits clear once the appropriate interrupt has been serviced and cleared,
as long as no additional, unmasked interrupt condition is present in the associated status register. Status bits that
have been masked via the Receive Interrupt Mask (RIMx) registers will also be masked from the RIIR register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC).
Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC).
Bit 5: Receive Loss of Signal Condition Clear (RLOSC).
Bit 4: Receive Loss of Frame Condition Clear (RLOFC).
Bit 3: Receive Remote Alarm Indication Condition Detect (RRAID).
Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD).
Bit 1: Receive Loss of Signal Condition Detect (RLOSD).
Bit 0: Receive Loss of Frame Condition Detect (RLOFD).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
RRAIC
—
7
0
7
0
RIIR
Receive Interrupt Information Register
09Fh + (200h x n): where n = 0 to 7, for Ports 1 to 8
RIM1
Receive Interrupt Mask Register 1
0A0h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RAISC
RLS7
6
0
6
0
RLOSC
RLS6*
5
0
5
0
RLOFC
166 of 276
RLS5
4
0
4
0
RRAID
RLS4
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
RAISD
RLS3
2
0
2
0
RLOSD
RLS2**
1
0
1
0
RLOFD
RLS1
0
0
0
0